Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

6 files changed, 31 insertions, 31 deletions

diff --git a/src/soc/qualcomm/qcs405/blsp.c b/src/soc/qualcomm/qcs405/blsp.c
index f185ea388a..42dc28d16c 100644
--- a/src/soc/qualcomm/qcs405/blsp.c
+++ b/src/soc/qualcomm/qcs405/blsp.c
@@ -59,7 +59,7 @@ blsp_return_t blsp_i2c_init(blsp_qup_id_t id)
 		return BLSP_ID_ERROR;
 
 	/* Configure Mini core to I2C core */
-	clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C);
+	clrsetbits32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C);
 
 	return BLSP_SUCCESS;
 }
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c
index 37fd2c2098..da2e8a4603 100644
--- a/src/soc/qualcomm/qcs405/clock.c
+++ b/src/soc/qualcomm/qcs405/clock.c
@@ -96,7 +96,7 @@ struct clock_config spi_cfg[] = {
 static int clock_configure_gpll0(void)
 {
 	/* Keep existing GPLL0 configuration, in RUN mode @800Mhz. */
-	setbits_le32(&gcc->gpll0.user_ctl,
+	setbits32(&gcc->gpll0.user_ctl,
 			1 << CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT |
 			1 << CLK_CTL_GPLL_PLLOUT_AUX2_SHFT |
 			1 << CLK_CTL_GPLL_PLLOUT_AUX_SHFT |
@@ -144,7 +144,7 @@ static int clock_configure(struct qcs405_clock *clk,
 				clk_cfg[idx].d_2);
 
 	/* Commit config to RCG*/
-	setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT));
+	setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT));
 
 	return 0;
 }
@@ -159,7 +159,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr,
 {
 
 	/* Set clock vote bit */
-	setbits_le32(vote_addr, BIT(vote_bit));
+	setbits32(vote_addr, BIT(vote_bit));
 
 	/* Ensure clock is enabled */
 	while (clock_is_off(cbcr_addr));
@@ -171,7 +171,7 @@ static int clock_enable(void *cbcr_addr)
 {
 
 	/* Set clock enable bit */
-	setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
+	setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
 
 	/* Ensure clock is enabled */
 	while (clock_is_off(cbcr_addr))
@@ -184,7 +184,7 @@ static int clock_disable(void *cbcr_addr)
 {
 
 	/* Set clock enable bit */
-	clrbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
+	clrbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
 	return 0;
 }
 
@@ -193,9 +193,9 @@ int clock_reset_bcr(void *bcr_addr, bool reset)
 	struct qcs405_bcr *bcr = bcr_addr;
 
 	if (reset)
-		setbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
+		setbits32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
 	else
-		clrbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
+		clrbits32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
 
 	return 0;
 }
diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c
index fc58fae7ff..19027c32bb 100644
--- a/src/soc/qualcomm/qcs405/gpio.c
+++ b/src/soc/qualcomm/qcs405/gpio.c
@@ -78,9 +78,9 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull)
 	gpio_configure(gpio, GPIO_FUNC_GPIO,
 				pull, GPIO_2MA, GPIO_DISABLE);
 
-	clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK <<
+	clrsetbits32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK <<
 		GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT);
-	clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE
+	clrsetbits32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE
 		<< GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE
 		<< GPIO_INTR_RAW_STATUS_EN_SHIFT);
 }
diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h
index 2ed3e10f76..7d948ec46e 100644
--- a/src/soc/qualcomm/qcs405/include/soc/iomap.h
+++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h
@@ -48,8 +48,8 @@
  */
 #define readl_i(a)           read32((const void *)(a))
 #define writel_i(v, a)       write32((void *)a, v)
-#define clrsetbits_le32_i(addr, clear, set)  \
-	clrsetbits_le32(((void *)(addr)), (clear), (set))
+#define clrsetbits32_i(addr, clear, set)  \
+	clrsetbits32(((void *)(addr)), (clear), (set))
 
 #define GCC_CLK_CTL_REG			((void *)0x01800000u)
 #define MSM_CLK_CTL_BASE		GCC_CLK_CTL_REG
diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c
index 827448ce91..f621778f65 100644
--- a/src/soc/qualcomm/qcs405/spi.c
+++ b/src/soc/qualcomm/qcs405/spi.c
@@ -247,10 +247,10 @@ static void write_force_cs(const struct spi_slave *slave, int assert)
 {
 	struct qcs_spi_slave *ds = to_qcs_spi(slave);
 	if (assert)
-		clrsetbits_le32(ds->regs->io_control,
+		clrsetbits32(ds->regs->io_control,
 			SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN);
 	else
-		clrsetbits_le32(ds->regs->io_control,
+		clrsetbits32(ds->regs->io_control,
 			SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS);
 }
 
@@ -275,7 +275,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds)
 	 * Configure Mini core to SPI core with Input Output enabled,
 	 * SPI master, N = 8 bits
 	 */
-	clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
+	clrsetbits32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
 						QUP_CONF_INPUT_MSK |
 						QUP_CONF_OUTPUT_MSK |
 						QUP_CONF_N_MASK,
@@ -288,7 +288,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds)
 	 * Configure Input first SPI protocol,
 	 * SPI master mode and no loopback
 	 */
-	clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
+	clrsetbits32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
 						SPI_CONFIG_NO_SLAVE_OPER_MSK,
 						SPI_CONFIG_NO_LOOP_BACK |
 						SPI_CONFIG_NO_SLAVE_OPER);
@@ -308,7 +308,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds)
 	 * INPUT_MODE = Block Mode
 	 * OUTPUT MODE = Block Mode
 	 */
-	clrsetbits_le32(ds->regs->qup_io_modes,
+	clrsetbits32(ds->regs->qup_io_modes,
 				QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK |
 				QUP_IO_MODES_INPUT_MODE_MSK |
 				QUP_IO_MODES_OUTPUT_MODE_MSK,
@@ -433,18 +433,18 @@ static void enable_io_config(struct qcs_spi_slave *ds,
 {
 
 	if (write_cnt) {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
 	} else {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
 	}
 
 	if (read_cnt) {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
 	} else {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
 	}
 }
diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c
index a94973ff2b..7ddfaa231e 100644
--- a/src/soc/qualcomm/qcs405/usb.c
+++ b/src/soc/qualcomm/qcs405/usb.c
@@ -183,16 +183,16 @@ static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3)
 static void setup_dwc3(struct usb_dwc3 *dwc3)
 {
 	/* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */
-	clrsetbits_le32(&dwc3->usb3pipectl,
+	clrsetbits32(&dwc3->usb3pipectl,
 		DWC3_GUSB3PIPECTL_DELAYP1TRANS,
 		DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX);
 
-	clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
+	clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
 			DWC3_GCTL_DISSCRAMBLE),
 			DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG);
 
 	/* configure controller in Host mode */
-	clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
+	clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
 			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));
 	printk(BIOS_INFO, "Configure USB in Host mode\n");
 }
@@ -213,10 +213,10 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data)
 
 	if (port == HSUSB_SS_PORT_0) {
 		/* Set PHY reset. */
-		setbits_le32(&dwc3->usb2_phy_bcr, BIT(1));
+		setbits32(&dwc3->usb2_phy_bcr, BIT(1));
 		udelay(15);
 		/* Clear PHY reset. */
-		clrbits_le32(&dwc3->usb2_phy_bcr, BIT(1));
+		clrbits32(&dwc3->usb2_phy_bcr, BIT(1));
 	} else {
 		clock_reset_bcr(dwc3->usb2_phy_bcr, 1);
 		udelay(15);
@@ -229,13 +229,13 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data)
 
 	if (port == HSUSB_SS_PORT_0) {
 		/* Set PHY POR reset. */
-		setbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0));
+		setbits32(&dwc3->usb2_phy_por_bcr, BIT(0));
 		val = read8(&dwc3->usb2_phy_dig->ctrl_common0);
 		val &= ~(0x4);
 		write8(&dwc3->usb2_phy_dig->ctrl_common0, val);
 		udelay(20);
 		/* Clear PHY POR reset. */
-		clrbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0));
+		clrbits32(&dwc3->usb2_phy_por_bcr, BIT(0));
 	} else {
 		clock_reset_bcr(dwc3->usb2_phy_por_bcr, 1);
 		val = read8(&dwc3->usb2_phy_dig->ctrl_common0);
@@ -254,13 +254,13 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data)
 	 */
 
 	 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
-	setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
+	setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
 			PIPE_UTMI_CLK_DIS);
 	udelay(2);
-	setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
+	setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
 			PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
 	udelay(3);
-	clrbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
+	clrbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
 			PIPE_UTMI_CLK_DIS);
 
 	printk(BIOS_INFO, "DWC3 and PHY setup finished\n");