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| author | Anil Kumar <anil.kumar.k@intel.com> | 2023-04-26 11:31:20 -0700 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2023-05-01 14:42:53 +0000 |
| commit | afb926ab0ab1405cb89245970073704cc9d2af83 (patch) | |
| tree | b2b594df83876fa771049e631f49885acbd6a7bb /src/soc/qualcomm/qcs405/gpio.c | |
| parent | 042ac352eaa97add631abe9f5c811f79209a2a2f (diff) | |
soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW Sync
The change 'commit Iac37aaa5ede5e1cd ("Add Kconfigs to indicate
when CSE FW sync is performed")' adds support to choose CSE FW update
to be performed in ROMSTAGE or RAMSTAGE. The patch also introduced a
dependency on ME_RW firmware compression.
This patch removes the dependency between CSE FW sync in RAMSTAGE and
ME_RW firmware compression as these two are not related and should be
decoupled to support CSE FW sync in RAMSTAGE without the requirement
to compress ME_FW.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74796
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Diffstat (limited to 'src/soc/qualcomm/qcs405/gpio.c')
0 files changed, 0 insertions, 0 deletions