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| author | Alexander Couzens <lynxis@fe80.eu> | 2023-12-01 16:46:24 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-09-30 11:11:21 +0000 |
| commit | 544fb8c296dd1a7d42e8795aa7f7479c0fd67b35 (patch) | |
| tree | ec7e3c600e328a00f8b293e92fffbfd770863dea /src/soc/qualcomm/ipq806x/spi.c | |
| parent | ced0c208e43ebcdf9560754a6db27d10ae7df81f (diff) | |
inteltool: elkhartlake: keep the same names as coreboot code uses
coreboot doesn't have a leading zero in gpio < 10.
E.g. G00 -> G0
Change-Id: I4558cec444ae2a081fbc0f49464354df222be6c9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84190
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/spi.c')
0 files changed, 0 insertions, 0 deletions