diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-04-09 19:23:04 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2014-11-13 06:29:16 +0100 |
| commit | f4b209f19c26fb0a09993947face5b7e5b175141 (patch) | |
| tree | b0e92332d38b05fab27eaf570434a1ba28fc8644 /src/soc/qualcomm/ipq806x/include/iomap.h | |
| parent | 028d816fe53f517401e7d021166356561c81477b (diff) | |
ipq8064: Make timer code compile
Commment out nonessential timer services and modify the source code to
cleanly build in coeboot environment. Do not remove dead code just
yet, these functions might be necessary later.
Need to rename the soc timer.h to prevent collisions with timer.h in
the top level include directory.
Currently build timer code for ramstage only.
BUG=chrome-os-partner:27784
TEST='emerge-storm coreboot' still succeeds
Original-Change-Id: Ib10133ccb42697840708845a8ea6d75ceeaeb3d5
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/194067
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 987ce95220953c16216d1e1d70d5a941d05fc9bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia9cf175da11c70709354def5e51bf79df4fda2fe
Reviewed-on: http://review.coreboot.org/7269
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/ipq806x/include/iomap.h')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/iomap.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/qualcomm/ipq806x/include/iomap.h b/src/soc/qualcomm/ipq806x/include/iomap.h index 5fcfde9ee7..8642410616 100644 --- a/src/soc/qualcomm/ipq806x/include/iomap.h +++ b/src/soc/qualcomm/ipq806x/include/iomap.h @@ -43,6 +43,8 @@ */ #define readl_i(a) read32((const void *)(a)) #define writel_i(v,a) write32(v,(void *)a) +#include <arch/io.h> +#include <cdp.h> #define MSM_CLK_CTL_BASE 0x00900000 @@ -50,7 +52,7 @@ #define MSM_GPT_BASE (MSM_TMR_BASE + 0x04) #define MSM_DGT_BASE (MSM_TMR_BASE + 0x24) -#define GPT_REG(off) (MSM_GPT_BASE + (off)) +#define GPT_REG(off) (((uint8_t *)(MSM_GPT_BASE)) + (off)) #define DGT_REG(off) (MSM_DGT_BASE + (off)) #define APCS_WDT0_EN (MSM_TMR_BASE + 0x0040) |