diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-05-13 17:47:57 -0700 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-01-03 04:59:50 +0100 |
| commit | 41a5d0df58754b75cfe5c79271ae383f3d5976c1 (patch) | |
| tree | a8138c4e6ea63d459103c43399bb5ccaa1b60e70 /src/soc/qualcomm/ipq806x/Makefile.inc | |
| parent | 1ea568586264946d357cc481447ed6395a129640 (diff) | |
ipq8064: add SOC initialization skeleton
The main benefit of adding this skeleton is the addition of the
correct memory map to CBMEM. Attempts to load depthcharge do not fail
because of unavailability of the bounce buffer.
BUG=chrome-os-partner:27784
TEST=boot updated firmware on AP148, observe
CPU: Qualcomm 8064
in the ramstage console output as well as not failing to load
depthcharge any more.
Original-Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199675
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a8fdbdd268a2bba1405d585881eb95510ad17a2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7b982f222ac3b93371fe77961f18719c5d269013
Reviewed-on: http://review.coreboot.org/8000
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/qualcomm/ipq806x/Makefile.inc')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 91cdd935da..f6acbed4ca 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -34,6 +34,7 @@ romstage-y += cbmem.c ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c +ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c |