From 41a5d0df58754b75cfe5c79271ae383f3d5976c1 Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Tue, 13 May 2014 17:47:57 -0700 Subject: ipq8064: add SOC initialization skeleton The main benefit of adding this skeleton is the addition of the correct memory map to CBMEM. Attempts to load depthcharge do not fail because of unavailability of the bounce buffer. BUG=chrome-os-partner:27784 TEST=boot updated firmware on AP148, observe CPU: Qualcomm 8064 in the ramstage console output as well as not failing to load depthcharge any more. Original-Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8 Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/199675 Original-Reviewed-by: Aaron Durbin (cherry picked from commit a8fdbdd268a2bba1405d585881eb95510ad17a2a) Signed-off-by: Marc Jones Change-Id: I7b982f222ac3b93371fe77961f18719c5d269013 Reviewed-on: http://review.coreboot.org/8000 Reviewed-by: Edward O'Callaghan Tested-by: build bot (Jenkins) --- src/soc/qualcomm/ipq806x/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/soc/qualcomm/ipq806x/Makefile.inc') diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 91cdd935da..f6acbed4ca 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -34,6 +34,7 @@ romstage-y += cbmem.c ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c +ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c -- cgit v1.2.3