diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-03-19 14:29:48 -0700 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-09-25 19:05:46 +0200 |
| commit | 765705789213e1914cad540bb7868d2154cdbedf (patch) | |
| tree | 9f00ea9aa62be2ea226027ff9eb3d2607b8ca458 /src/soc/qualcomm/ipq806x/Kconfig | |
| parent | 6481cfb15d62784b87eabe972a742fa1e3da129d (diff) | |
soc/qualcomm: Add generic support skeleton for ipq806x
Skeleton for soc ipq806x
Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/190723
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911)
soc/ipq806x: Disable LPAE mode.
LPAE (large physical address extension) is not available on this SOC
core, do not enable it.
Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b
Signed-off-by: Deepa Dinamani <deepad@codeaurora.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198023
Reviewed-by: deepa dinamani <deepad@quicinc.com>
(cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b)
Squashed 2 commits for the Qualcomm ipq806x SOC.
Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6963
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/qualcomm/ipq806x/Kconfig')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/Kconfig | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig new file mode 100644 index 0000000000..fcf8ccdeae --- /dev/null +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -0,0 +1,22 @@ +config SOC_QC_IPQ806X + select ARCH_BOOTBLOCK_ARMV4 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 + bool + default n + +if SOC_QC_IPQ806X + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x18000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" + default 0x18080 + +endif |