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authorSeunghwan Kim <sh_.kim@samsung.corp-partner.google.com>2024-03-25 08:57:09 +0900
committerMartin L Roth <gaumless@gmail.com>2024-04-01 04:53:11 +0000
commit2cb83125bb73f2c9b63519ccc05deb5c7adf690e (patch)
tree1f080c6c5f7267421d1c01e0fe501c4081e60461 /src/soc/qualcomm/ipq40xx/i2c.c
parentf3b2c6e5dda795f9e06abf366d4d874c19c5bd27 (diff)
mb/google/{brya,hades}: use soc index for variant_update_power_limits()
The power_limits_config variable for ADL/RPL is array data, but we got soc_power_limits_config variable without its index. So correct the code to get the proper pointer of the data for current CPU SKU. I tried to override the PL4 value to 80W from 114W with following table in ramstage.c as a test for bug b/328729536. ``` const struct cpu_power_limits limits[] = { {PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000}, } ``` And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool. - Before this patch: msr_pl4 was not changed, it's always 114 - After this patch: msr_pl4 was changed to 80 BUG=None BRANCH=None TEST=Built and tested the function could adjust PL4 on xol in local. Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/soc/qualcomm/ipq40xx/i2c.c')
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