tegra124/nyan: various fixes and additions

Tegra124: SDMMC: Configure base clock frequency.
Reviewed-on: https://chromium-review.googlesource.com/173841
(cherry picked from commit d3157e9a380cfb018cc69a1f23f277c3c5b680a6)

Tegra124: SDMMC: Configure pinmux for MMC 3/4.
Reviewed-on: https://chromium-review.googlesource.com/174011
(cherry picked from commit 55af9a86a56d6bc0ce9bcff4fd5226a60ae2033b)

tegra124: Move DMA-related #defines and definitions to header
Reviewed-on: https://chromium-review.googlesource.com/174444
(cherry picked from commit 9d917927a5b7151958289469b9049ac91efa41e3)

tegra124: Assign console address for kernel.
Reviewed-on: https://chromium-review.googlesource.com/174486
(cherry picked from commit 36e9370f30bd173879958d164156997841ec4e9c)

nyan: Fix up the gpio indices in chromeos.c.
Reviewed-on: https://chromium-review.googlesource.com/174418
(cherry picked from commit fba4ae1080c19f11abe1205b871ada14db996c61)

Nyan: turn on the backlight.
Reviewed-on: https://chromium-review.googlesource.com/174533
(cherry picked from commit 12649c9611981dd8d6567ba0238c8b8247c52215)

tegra124: Fix the disp1 source field.
Reviewed-on: https://chromium-review.googlesource.com/174701
(cherry picked from commit eed380e09075e1eef0bde7d1bb15c4343f30bfe0)

nyan: set up the aux channel i2c interface
Reviewed-on: https://chromium-review.googlesource.com/174620
(cherry picked from commit ea81cb44a1c11cd78643c69ac818304cd393749e)

tegra124: fix typos in the clock code.
Reviewed-on: https://chromium-review.googlesource.com/174684
(cherry picked from commit 72365c33693db4eb6e01032938221f592b7e5a02)

tegra124: Revamp clock source/divisor configuration
Reviewed-on: https://chromium-review.googlesource.com/174804
(cherry picked from commit 3f31a634f69595bcc6a473301d1492c97a767809)

tegra: Add gpio_output_open_drain() function
Reviewed-on: https://chromium-review.googlesource.com/174650
(cherry picked from commit bc1c28926810e722e9b82339ea0585d083e3fa8c)

tegra124: add nvidia-generated files
Reviewed-on: https://chromium-review.googlesource.com/174610
(cherry picked from commit 7706f3200f7fc11b7a443f336bff6a37afa94652)

nyan: Ignore the dev mode GPIO.
Reviewed-on: https://chromium-review.googlesource.com/174837
(cherry picked from commit 9513e608f3063fdb3e9d8bd04e6e5fe35a5bfcee)

Tegra124: Add support for the ARM architectural timer.
Reviewed-on: https://chromium-review.googlesource.com/174835
(cherry picked from commit 25a91fcf7e79cc450caa59bc6b65f954bb96ac6c)

nyan: Initialize the ARM architectural timer in the RAM stage.
Reviewed-on: https://chromium-review.googlesource.com/174836
(cherry picked from commit 581f592c12de91c0cf8279ede2850e38dd0cd2e8)

tegra124: nyan: Move mainboard level clock stuff into the mainboard source.
Reviewed-on: https://chromium-review.googlesource.com/174843
(cherry picked from commit 5ab100b0bad22814261f9b755b59394562c9145a)

tegra124: add some explanatory text about U7.1 computations.
Reviewed-on: https://chromium-review.googlesource.com/173910
(cherry picked from commit 822cad0ceeceeb5160c8216e05eec13fd04a6413)

Set the EC SPI clock source to PLLP and divide down to around 5MHz
Reviewed-on: https://chromium-review.googlesource.com/173954
(cherry picked from commit c0e22d76d3887ca1f727443a47db38dec12c0b74)

nyan: Move non-essential configuration out of bootblock and into ram stage.
Reviewed-on: https://chromium-review.googlesource.com/174844
(cherry picked from commit dad7f68c76f7b83edacd8b22c9dbd3f0ff027397)

tegra124: clocks: Save some IOs in clock_enable_clear_reset.
Reviewed-on: https://chromium-review.googlesource.com/174845
(cherry picked from commit 81b977a2758d42471667e2cbe31f160dfda5bca4)

tegra124: re-write SPI driver w/ full duplex support
Reviewed-on: https://chromium-review.googlesource.com/174446
(cherry picked from commit 51c9a34240d6a068780a7d1c27b032b56b2d3e54)

tegra124: move SPI-related structures from .c to .h
Reviewed-on: https://chromium-review.googlesource.com/174637
(cherry picked from commit 36760a4463c2c33f494ca7ea5a36810fa4502058)

tegra124: add frame header info to SPI channel struct
Reviewed-on: https://chromium-review.googlesource.com/174638
(cherry picked from commit e24773eb946e2c4cb5e828f055d45d92bd1a4f9f)

tegra124: re-factor tegra_spi_init()
Reviewed-on: https://chromium-review.googlesource.com/174639
(cherry picked from commit 88354b996459a702c36604f5f92c24e63df8de7e)

nyan: Set CrOS EC frame header parameters for SPI
Reviewed-on: https://chromium-review.googlesource.com/174710
(cherry picked from commit 29173ba5863eebb2864a8384435cde2f0d5ca233)

tegra124: Add Rx frame header support to SPI code
Reviewed-on: https://chromium-review.googlesource.com/174711
(cherry picked from commit 1d1630e770804649ef74d31db194d3bde9968832)

tegra124: add support for the Serial Output Resource (sor)
Reviewed-on: https://chromium-review.googlesource.com/174612
(cherry picked from commit 3eebd10afea4498380582e04560af89126911ed9)

nyan: tegra124: Enable I, D and L2 caches in romstage.
Reviewed-on: https://chromium-review.googlesource.com/173777
(cherry picked from commit 74512b7ecfbd50f01a25677307084699ee8c6007)

tegra and tegra124: Bring up graphics
Reviewed-on: https://chromium-review.googlesource.com/174613
(cherry picked from commit 7e944208a176cdac44a31e2a9961c8bd5dc4ece8)

nyan: Move the DMA memory region.
Reviewed-on: https://chromium-review.googlesource.com/174953
(cherry picked from commit c66e22859252eaebceb07a3118ac61f4cf6289eb)

tegra124: Increase CBFS cache buffer size
Reviewed-on: https://chromium-review.googlesource.com/174950
(cherry picked from commit 6dbb4e5f0d66c68df45ac73e3f223b856b715026)

tegra124: Add USB PLL, PHY and EHCI setup code
Reviewed-on: https://chromium-review.googlesource.com/174651
(cherry picked from commit ecd5c398ff6748a7d40089019471357b58d3a6ea)

tegra124: add in some undocument clock source and PLL registers
Reviewed-on: https://chromium-review.googlesource.com/174948
(cherry picked from commit 73fcc4981da6e4415b514eaafb42bc265ab0cd9a)

tegra124: small cleanups of the code
Reviewed-on: https://chromium-review.googlesource.com/174995
(cherry picked from commit 7256aba07e9567ef8d73f05e1f80c4d45fd57bda)

Squashed 34 commits for tegra124 / nyan support.

Change-Id: I050c7ad962e0d24550b0b33c9318e89c80d01f00
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6870
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)

7 files changed, 1158 insertions, 6 deletions

diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h
index 33dbe53ff1..dac2065f5b 100644
--- a/src/soc/nvidia/tegra/dc.h
+++ b/src/soc/nvidia/tegra/dc.h
@@ -561,4 +561,5 @@ struct disp_ctl_win {
 };
 
 void display_startup(device_t dev);
+void dp_bringup(u32 winb_addr);
 #endif /* __SOC_NVIDIA_TEGRA_DC_H */
diff --git a/src/soc/nvidia/tegra/displayport.h b/src/soc/nvidia/tegra/displayport.h
new file mode 100644
index 0000000000..8a57170bf9
--- /dev/null
+++ b/src/soc/nvidia/tegra/displayport.h
@@ -0,0 +1,316 @@
+/*
+ * drivers/video/tegra/dc/dpaux_regs.h
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__
+#define __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__
+
+/* things we can't get rid of just yet. */
+#define DPAUX_INTR_EN_AUX				(0x1)
+#define DPAUX_INTR_AUX					(0x5)
+#define DPAUX_DP_AUXDATA_WRITE_W(i)		     (0x9 + 4*(i))
+#define DPAUX_DP_AUXDATA_READ_W(i)		     (0x19 + 4*(i))
+#define DPAUX_DP_AUXADDR				(0x29)
+#define DPAUX_DP_AUXCTL					(0x2d)
+#define DPAUX_DP_AUXCTL_CMDLEN_SHIFT			(0)
+#define DPAUX_DP_AUXCTL_CMDLEN_FIELD			(0xff)
+#define DPAUX_DP_AUXCTL_CMD_SHIFT			(12)
+#define DPAUX_DP_AUXCTL_CMD_MASK			(0xf << 12)
+#define DPAUX_DP_AUXCTL_CMD_I2CWR			(0 << 12)
+#define DPAUX_DP_AUXCTL_CMD_I2CRD			(1 << 12)
+#define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT			(2 << 12)
+#define DPAUX_DP_AUXCTL_CMD_MOTWR			(4 << 12)
+#define DPAUX_DP_AUXCTL_CMD_MOTRD			(5 << 12)
+#define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT			(6 << 12)
+#define DPAUX_DP_AUXCTL_CMD_AUXWR			(8 << 12)
+#define DPAUX_DP_AUXCTL_CMD_AUXRD			(9 << 12)
+#define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT		(16)
+#define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK		(0x1 << 16)
+#define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE		(0 << 16)
+#define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING		(1 << 16)
+#define DPAUX_DP_AUXCTL_RST_SHIFT			(31)
+#define DPAUX_DP_AUXCTL_RST_DEASSERT			(0 << 31)
+#define DPAUX_DP_AUXCTL_RST_ASSERT			(1 << 31)
+#define DPAUX_DP_AUXSTAT				(0x31)
+#define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT		(28)
+#define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG		(0 << 28)
+#define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED		(1 << 28)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT		(20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK		(0xf << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE		(0 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC		(1 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1		(2 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND		(3 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS		(4 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH		(5 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1		(6 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1		(7 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M		(8 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1		(9 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2		(10 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY		(11 << 20)
+#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP		(12 << 20)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT		(16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK			(0xf << 16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK			(0 << 16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK			(1 << 16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER		(2 << 16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK		(4 << 16)
+#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER		(8 << 16)
+#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT		(11)
+#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING	(0 << 11)
+#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING		(1 << 11)
+#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT		(10)
+#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING	(0 << 10)
+#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING		(1 << 10)
+#define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT			(9)
+#define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING		(0 << 9)
+#define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING		(1 << 9)
+#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT		(8)
+#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING	(0 << 8)
+#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING		(1 << 8)
+#define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT			(0)
+#define DPAUX_DP_AUXSTAT_REPLY_M_MASK			(0xff << 0)
+#define DPAUX_HPD_CONFIG				(0x3d)
+#define DPAUX_HPD_IRQ_CONFIG				(0x41)
+#define DPAUX_DP_AUX_CONFIG				(0x45)
+#define DPAUX_HYBRID_PADCTL				(0x49)
+#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT	(15)
+#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE	(0 << 15)
+#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE	(1 << 15)
+#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT	(14)
+#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE	(0 << 14)
+#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE	(1 << 14)
+#define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT		(12)
+#define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK	(0x3 << 12)
+#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60		(0 << 12)
+#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64		(1 << 12)
+#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70		(2 << 12)
+#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56		(3 << 12)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT		(8)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK	(0x7 << 8)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78		(0 << 8)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60		(1 << 8)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54		(2 << 8)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45		(3 << 8)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50		(4 << 8)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42		(5 << 8)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39		(6 << 8)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34		(7 << 8)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT		(2)
+#define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK	(0x3f << 2)
+#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT		(1)
+#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE	(0 << 1)
+#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE	(1 << 1)
+#define DPAUX_HYBRID_PADCTL_MODE_SHIFT			(0)
+#define DPAUX_HYBRID_PADCTL_MODE_AUX			(0)
+#define DPAUX_HYBRID_PADCTL_MODE_I2C			(1)
+#define DPAUX_HYBRID_SPARE				(0x4d)
+#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP		(0)
+#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN		(1)
+
+/* TODO: figure out which of the NV_ constants are the same as all the other
+ * display port standard constants.
+ */
+
+#define DP_AUX_DEFER_MAX_TRIES		7
+#define DP_AUX_TIMEOUT_MAX_TRIES	2
+#define DP_POWER_ON_MAX_TRIES		3
+#define DP_CLOCK_RECOVERY_MAX_TRIES	7
+#define DP_CLOCK_RECOVERY_TOT_TRIES	15
+
+#define DP_AUX_MAX_BYTES		16
+
+#define DP_LCDVCC_TO_HPD_DELAY_MS	200
+#define DP_AUX_TIMEOUT_MS		40
+#define DP_DPCP_RETRY_SLEEP_NS		400
+
+enum {
+	driveCurrent_Level0 = 0,
+	driveCurrent_Level1 = 1,
+	driveCurrent_Level2 = 2,
+	driveCurrent_Level3 = 3,
+};
+
+enum {
+	preEmphasis_Disabled = 0,
+	preEmphasis_Level1   = 1,
+	preEmphasis_Level2   = 2,
+	preEmphasis_Level3   = 3,
+};
+
+enum {
+	postCursor2_Level0 = 0,
+	postCursor2_Level1 = 1,
+	postCursor2_Level2 = 2,
+	postCursor2_Level3 = 3,
+	postCursor2_Supported
+};
+
+
+/* the +10ms is the time for power rail going up from 10-90% or
+   90%-10% on powerdown */
+/* Time from power-rail is turned on and aux/12c-over-aux is available */
+#define EDP_PWR_ON_TO_AUX_TIME_MS	    (200+10)
+/* Time from power-rail is turned on and MainLink is available for LT */
+#define EDP_PWR_ON_TO_ML_TIME_MS	    (200+10)
+/* Time from turning off power to turn-it on again (does not include post
+   poweron time) */
+#define EDP_PWR_OFF_TO_ON_TIME_MS	    (500+10)
+
+struct tegra_dc_dp_data {
+	struct tegra_dc			*dc;
+	struct tegra_dc_sor_data	*sor;
+	void				*aux_base;
+	struct tegra_dc_mode		*mode;
+	struct tegra_dc_dp_link_config	 link_cfg;
+};
+
+
+/* DPCD definitions */
+/* you know, all the vendors pick their own set of defines.
+ * All of them.
+ * FIXME so we can use the ones in include/device/drm_dp_helper.h
+ */
+#define NV_DPCD_REV					(0x00000000)
+#define NV_DPCD_REV_MAJOR_SHIFT				(4)
+#define NV_DPCD_REV_MAJOR_MASK				(0xf << 4)
+#define NV_DPCD_REV_MINOR_SHIFT				(0)
+#define NV_DPCD_REV_MINOR_MASK				(0xf)
+#define NV_DPCD_MAX_LINK_BANDWIDTH			(0x00000001)
+#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GPBS	(0x00000006)
+#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GPBS	(0x0000000a)
+#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GPBS	(0x00000014)
+#define NV_DPCD_MAX_LANE_COUNT				(0x00000002)
+#define NV_DPCD_MAX_LANE_COUNT_MASK			(0x1f)
+#define NV_DPCD_MAX_LANE_COUNT_LANE_1			(0x00000001)
+#define NV_DPCD_MAX_LANE_COUNT_LANE_2			(0x00000002)
+#define NV_DPCD_MAX_LANE_COUNT_LANE_4			(0x00000004)
+#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO	(0x00000000 << 7)
+#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES	(0x00000001 << 7)
+#define NV_DPCD_MAX_DOWNSPREAD				(0x00000003)
+#define NV_DPCD_MAX_DOWNSPREAD_VAL_NONE			(0x00000000)
+#define NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT		(0x00000001)
+#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F	(0x00000000 << 6)
+#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T	(0x00000001 << 6)
+#define NV_DPCD_EDP_CONFIG_CAP				(0x0000000D)
+#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_NO		(0x00000000)
+#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES		(0x00000001)
+#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO	(0x00000000 << 1)
+#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES	(0x00000001 << 1)
+#define NV_DPCD_LINK_BANDWIDTH_SET			(0x00000100)
+#define NV_DPCD_LANE_COUNT_SET				(0x00000101)
+#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F	(0x00000000 << 7)
+#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T	(0x00000001 << 7)
+#define NV_DPCD_TRAINING_PATTERN_SET			(0x00000102)
+#define NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK		0x3
+#define NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE		(0x00000000)
+#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1		(0x00000001)
+#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2		(0x00000002)
+#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3		(0x00000003)
+#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F	(0x00000000 << 5)
+#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T	(0x00000001 << 5)
+#define NV_DPCD_TRAINING_LANE0_SET			(0x00000103)
+#define NV_DPCD_TRAINING_LANE1_SET			(0x00000104)
+#define NV_DPCD_TRAINING_LANE2_SET			(0x00000105)
+#define NV_DPCD_TRAINING_LANE3_SET			(0x00000106)
+#define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT		0
+#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T	(0x00000001 << 2)
+#define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT		3
+#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T	(0x00000001 << 5)
+#define NV_DPCD_DOWNSPREAD_CTRL				(0x00000107)
+#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE		(0x00000000 << 4)
+#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5	(0x00000001 << 4)
+#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET		(0x00000108)
+#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B	1
+#define NV_DPCD_EDP_CONFIG_SET				(0x0000010A)
+#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE	(0x00000000)
+#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE		(0x00000001)
+#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE	(0x00000000 << 1)
+#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE	(0x00000001 << 1)
+#define NV_DPCD_TRAINING_LANE0_1_SET2			(0x0000010F)
+#define NV_DPCD_TRAINING_LANE2_3_SET2			(0x00000110)
+#define NV_DPCD_LANEX_SET2_PC2_SHIFT			0
+#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T		(0x00000001 << 2)
+#define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT		4
+#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T	(0x00000001 << 6)
+#define NV_DPCD_SINK_COUNT				(0x00000200)
+#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR		(0x00000201)
+#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO	(0x00000000 << 1)
+#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES	(0x00000001 << 1)
+#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO		(0x00000000 << 2)
+#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES	(0x00000001 << 2)
+#define NV_DPCD_LANE0_1_STATUS				(0x00000202)
+#define NV_DPCD_LANE2_3_STATUS				(0x00000203)
+#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT		0
+#define NV_DPCD_STATUS_LANEX_CR_DONE_NO			(0x00000000)
+#define NV_DPCD_STATUS_LANEX_CR_DONE_YES		(0x00000001)
+#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT		1
+#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO		(0x00000000 << 1)
+#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES		(0x00000001 << 1)
+#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT	2
+#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO		(0x00000000 << 2)
+#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES		(0x00000001 << 2)
+#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT		4
+#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO		(0x00000000 << 4)
+#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES		(0x00000001 << 4)
+#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT	5
+#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO	(0x00000000 << 5)
+#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES	(0x00000001 << 5)
+#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT	6
+#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO	(0x00000000 << 6)
+#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES	(0x00000001 << 6)
+#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED		(0x00000204)
+#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO	(0x00000000)
+#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES	(0x00000001)
+#define NV_DPCD_LANE0_1_ADJUST_REQ			(0x00000206)
+#define NV_DPCD_LANE2_3_ADJUST_REQ			(0x00000207)
+#define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT		0
+#define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK		0x3
+#define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT		2
+#define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK		(0x3 << 2)
+#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT		4
+#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK		(0x3 << 4)
+#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT		6
+#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK		(0x3 << 6)
+#define NV_DPCD_ADJUST_REQ_POST_CURSOR2			(0x0000020C)
+#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK	0x3
+#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i)	(i*2)
+#define NV_DPCD_TEST_REQUEST				(0x00000218)
+#define NV_DPCD_SOURCE_IEEE_OUI				(0x00000300)
+#define NV_DPCD_SINK_IEEE_OUI				(0x00000400)
+#define NV_DPCD_BRANCH_IEEE_OUI				(0x00000500)
+#define NV_DPCD_SET_POWER				(0x00000600)
+#define NV_DPCD_SET_POWER_VAL_RESERVED			(0x00000000)
+#define NV_DPCD_SET_POWER_VAL_D0_NORMAL			(0x00000001)
+#define NV_DPCD_SET_POWER_VAL_D3_PWRDWN			(0x00000002)
+#define NV_DPCD_HDCP_BKSV_OFFSET			(0x00068000)
+#define NV_DPCD_HDCP_RPRIME_OFFSET			(0x00068005)
+#define NV_DPCD_HDCP_AKSV_OFFSET			(0x00068007)
+#define NV_DPCD_HDCP_AN_OFFSET				(0x0006800C)
+#define NV_DPCD_HDCP_VPRIME_OFFSET			(0x00068014)
+#define NV_DPCD_HDCP_BCAPS_OFFSET			(0x00068028)
+#define NV_DPCD_HDCP_BSTATUS_OFFSET			(0x00068029)
+#define NV_DPCD_HDCP_BINFO_OFFSET			(0x0006802A)
+#define NV_DPCD_HDCP_KSV_FIFO_OFFSET			(0x0006802C)
+#define NV_DPCD_HDCP_AINFO_OFFSET			(0x0006803B)
+
+int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
+			u8 *data, u32 *size, u32 *aux_stat);
+int dpaux_write(u32 addr, u32 size, u32 data);
+int dpaux_read(u32 addr, u32 size, u8 *data);
+void debug_dpaux_print(u32 addr, u32 size);
+void dp_link_training(u32 lanes, u32 speed);
+#endif /* __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__ */
diff --git a/src/soc/nvidia/tegra/dp.c b/src/soc/nvidia/tegra/dp.c
new file mode 100644
index 0000000000..28e30c89c4
--- /dev/null
+++ b/src/soc/nvidia/tegra/dp.c
@@ -0,0 +1,586 @@
+/*
+ * drivers/video/tegra/dc/dp.c
+ *
+ * Copyright (c) 2011-2013, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/i2c.h>
+#include <stdlib.h>
+#include <string.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include "i2c.h"
+#include "dc.h"
+/* shit. This is broken. */
+#include <soc/nvidia/tegra124/sor.h>
+// this is really broken. #include <soc/ardpaux.h>
+#include <soc/nvidia/tegra/displayport.h>
+
+
+extern int dump;
+unsigned long READL(void* p);
+void WRITEL(unsigned long value, void* p);
+
+static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
+{
+	void *addr = dp->aux_base + (u32)(reg <<2);
+	u32 reg_val = READL(addr);
+	return reg_val;
+}
+
+static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
+	u32 reg, u32 val)
+{
+	void *addr = dp->aux_base + (u32)(reg <<2);
+	WRITEL(val, addr);
+}
+
+
+static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
+	u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
+{
+//	unsigned long	timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
+	u32		reg_val	   = 0;
+
+	printk(BIOS_SPEW, "JZ: %s: enter, poll_reg: %#x: timeout: 0x%x\n",
+		__func__, reg*4, timeout_ms);
+	do {
+//		udelay(poll_interval_us);
+		udelay(1);
+		reg_val = tegra_dpaux_readl(dp, reg);
+	} while (((reg_val & mask) != exp_val) && (--timeout_ms > 0));
+
+	if ((reg_val & mask) == exp_val)
+		return 0;	/* success */
+	printk(BIOS_SPEW,"dpaux_poll_register 0x%x: timeout: (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", reg, reg_val, mask, exp_val);
+	return timeout_ms;
+}
+
+
+static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
+{
+	/* According to DP spec, each aux transaction needs to finish
+	   within 40ms. */
+	if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
+			DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
+			DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
+			100, DP_AUX_TIMEOUT_MS*1000) != 0) {
+		printk(BIOS_SPEW,"dp: DPAUX transaction timeout\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
+	u32 addr, u8 *data, u32 *size, u32 *aux_stat)
+{
+	int	i;
+	u32	reg_val;
+	u32	timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
+	u32	defer_retries	= DP_AUX_DEFER_MAX_TRIES;
+	u32	temp_data;
+
+	if (*size > DP_AUX_MAX_BYTES)
+		return -1;	/* only write one chunk of data */
+
+	/* Make sure the command is write command */
+	switch (cmd) {
+	case DPAUX_DP_AUXCTL_CMD_I2CWR:
+	case DPAUX_DP_AUXCTL_CMD_MOTWR:
+	case DPAUX_DP_AUXCTL_CMD_AUXWR:
+		break;
+	default:
+		printk(BIOS_SPEW,"dp: aux write cmd 0x%x is invalid\n",
+			cmd);
+		return -1;
+	}
+
+#if 0
+/* interesting. */
+	if (tegra_platform_is_silicon()) {
+		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
+		if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
+			printk(BIOS_SPEW,"dp: HPD is not detected\n");
+			return -EFAULT;
+		}
+	}
+#endif
+
+	tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
+	for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i) {
+		memcpy(&temp_data, data, 4);
+		tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i),
+			temp_data);
+		data += 4;
+	}
+
+	reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
+	reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
+	reg_val |= cmd;
+	reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
+	reg_val |= ((*size-1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
+
+	while ((timeout_retries > 0) && (defer_retries > 0)) {
+		if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
+		    (defer_retries != DP_AUX_DEFER_MAX_TRIES))
+			udelay(1);
+
+		reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
+		tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
+
+		if (tegra_dpaux_wait_transaction(dp))
+			printk(BIOS_SPEW,"dp: aux write transaction timeout\n");
+
+		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
+
+		if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
+			(*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
+			(*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
+			(*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
+			if (timeout_retries-- > 0) {
+				printk(BIOS_SPEW,"dp: aux write retry (0x%x) -- %d\n",
+					*aux_stat, timeout_retries);
+				/* clear the error bits */
+				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+					*aux_stat);
+				continue;
+			} else {
+				printk(BIOS_SPEW,"dp: aux write got error (0x%x)\n",
+					*aux_stat);
+				return -1;
+			}
+		}
+
+		if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
+			(*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
+			if (defer_retries-- > 0) {
+				printk(BIOS_SPEW, "dp: aux write defer (0x%x) -- %d\n",
+					*aux_stat, defer_retries);
+				/* clear the error bits */
+				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+					*aux_stat);
+				continue;
+			} else {
+				printk(BIOS_SPEW, "dp: aux write defer exceeds max retries "
+					"(0x%x)\n",
+					*aux_stat);
+				return -1;
+			}
+		}
+
+		if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
+			DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
+			*size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
+			return 0;
+		} else {
+			printk(BIOS_SPEW,"dp: aux write failed (0x%x)\n", *aux_stat);
+			return -1;
+		}
+	}
+	/* Should never come to here */
+	return -1;
+}
+
+static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
+	u8 *data, u32 *size, u32 *aux_stat)
+{
+	u32	cur_size = 0;
+	u32	finished = 0;
+	u32	cur_left;
+	int	ret	 = 0;
+
+	do {
+		cur_size = *size - finished;
+		if (cur_size > DP_AUX_MAX_BYTES)
+			cur_size = DP_AUX_MAX_BYTES;
+		cur_left = cur_size;
+		ret = tegra_dc_dpaux_write_chunk(dp, cmd, addr,
+			data, &cur_left, aux_stat);
+
+		cur_size -= cur_left;
+		finished += cur_size;
+		addr += cur_size;
+		data += cur_size;
+
+		if (ret)
+			break;
+	} while (*size > finished);
+
+	*size = finished;
+	return ret;
+}
+
+static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
+	u32 addr, u8 *data, u32 *size, u32 *aux_stat)
+{
+	u32	reg_val;
+	u32	timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
+	u32	defer_retries	= DP_AUX_DEFER_MAX_TRIES;
+
+	if (*size > DP_AUX_MAX_BYTES)
+		return -1;	/* only read one chunk */
+
+	/* Check to make sure the command is read command */
+	switch (cmd) {
+	case DPAUX_DP_AUXCTL_CMD_I2CRD:
+	case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
+	case DPAUX_DP_AUXCTL_CMD_MOTRD:
+	case DPAUX_DP_AUXCTL_CMD_AUXRD:
+		break;
+	default:
+		printk(BIOS_SPEW,"dp: aux read cmd 0x%x is invalid\n", cmd);
+		return -1;
+	}
+
+	if (0){
+		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
+		if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
+			printk(BIOS_SPEW,"dp: HPD is not detected\n");
+			//return EFAULT;
+		}
+	}
+
+	tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
+
+	reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
+	reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
+	reg_val |= cmd;
+	printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
+	reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
+	reg_val |= ((*size-1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
+	printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
+	while ((timeout_retries > 0) && (defer_retries > 0)) {
+		if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
+		    (defer_retries != DP_AUX_DEFER_MAX_TRIES))
+			udelay(DP_DPCP_RETRY_SLEEP_NS * 2);
+
+		reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
+		printk(BIOS_SPEW, "cmd = %08x\n", reg_val);
+		tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
+
+		if (tegra_dpaux_wait_transaction(dp))
+			printk(BIOS_SPEW,"dp: aux read transaction timeout\n");
+
+		*aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
+		printk(BIOS_SPEW, "dp: %s: aux stat: 0x%08x\n", __func__, *aux_stat);
+
+		if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
+			(*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
+			(*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
+			(*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
+			if (timeout_retries-- > 0) {
+				printk(BIOS_SPEW, "dp: aux read retry (0x%x) -- %d\n",
+					*aux_stat, timeout_retries);
+				/* clear the error bits */
+				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+					*aux_stat);
+				continue; /* retry */
+			} else {
+				printk(BIOS_SPEW,"dp: aux read got error (0x%x)\n",
+					*aux_stat);
+				return -1;
+			}
+		}
+
+		if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
+			(*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
+			if (defer_retries-- > 0) {
+				printk(BIOS_SPEW, "dp: aux read defer (0x%x) -- %d\n",
+					*aux_stat, defer_retries);
+				/* clear the error bits */
+				tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
+					*aux_stat);
+				continue;
+			} else {
+				printk(BIOS_SPEW,"dp: aux read defer exceeds max retries "
+					"(0x%x)\n", *aux_stat);
+				return -1;
+			}
+		}
+
+		if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
+			DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
+			int i;
+			u32 temp_data[4];
+
+			for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i)
+				temp_data[i] = tegra_dpaux_readl(dp,
+					DPAUX_DP_AUXDATA_READ_W(i));
+
+			*size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
+			printk(BIOS_SPEW, "dp: aux read data %d bytes\n", *size);
+			memcpy(data, temp_data, *size);
+
+			return 0;
+		} else {
+			printk(BIOS_SPEW,"dp: aux read failed (0x%x\n", *aux_stat);
+			return -1;
+		}
+	}
+	/* Should never come to here */
+	printk(BIOS_SPEW, "%s: can't\n", __func__);
+	return -1;
+}
+
+int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
+	u8 *data, u32 *size, u32 *aux_stat)
+{
+	u32	finished = 0;
+	u32	cur_size;
+	int	ret	 = 0;
+
+	do {
+		cur_size = *size - finished;
+		if (cur_size > DP_AUX_MAX_BYTES)
+			cur_size = DP_AUX_MAX_BYTES;
+
+		ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,
+			data, &cur_size, aux_stat);
+
+		/* cur_size should be the real size returned */
+		addr += cur_size;
+		data += cur_size;
+		finished += cur_size;
+
+		if (ret)
+			break;
+
+#if 0
+		if (cur_size == 0) {
+			printk(BIOS_SPEW,"JZ: no data found, ret\n");
+			break;
+		}
+#endif
+	} while (*size > finished);
+
+	*size = finished;
+	return ret;
+}
+
+static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
+	u8 *data_ptr)
+{
+	u32 size = 1;
+	u32 status = 0;
+	int ret;
+
+	ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
+		cmd, data_ptr, &size, &status);
+	if (ret)
+		printk(BIOS_SPEW,"dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
+			cmd, status);
+
+	return ret;
+}
+
+static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
+	struct tegra_dc_dp_link_config *cfg)
+{
+	u8     dpcd_data;
+	int    ret;
+
+	ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
+				    &dpcd_data);
+	if (ret)
+		return ret;
+
+	cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
+	printk(BIOS_SPEW, "JZ: %s: max_lane_count: %d\n", __func__, cfg->max_lane_count);
+
+	cfg->support_enhanced_framing =
+		(dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
+	        1 : 0;
+	printk(BIOS_SPEW, "JZ: %s: enh-framing: %d\n", __func__, cfg->support_enhanced_framing);
+
+	ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
+				    &dpcd_data);
+	if (ret)
+		return ret;
+	cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
+		1 : 0;
+	printk(BIOS_SPEW, "JZ: %s: downspread: %d\n", __func__, cfg->downspread);
+
+	ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
+				    &cfg->max_link_bw);
+	if (ret)
+		return ret;
+	printk(BIOS_SPEW, "JZ: %s: max_link_bw: %d\n", __func__, cfg->max_link_bw);
+
+	// jz, changed
+	// cfg->bits_per_pixel = dp->dc->pdata->default_out->depth;
+	cfg->bits_per_pixel = 24;
+
+	/* TODO: need to come from the board file */
+	/* Venice2 settings */
+	cfg->drive_current = 0x20202020;
+	cfg->preemphasis = 0;
+	cfg->postcursor = 0;
+
+	ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
+				    &dpcd_data);
+	if (ret)
+		return ret;
+	cfg->alt_scramber_reset_cap =
+		(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
+		1 : 0;
+	cfg->only_enhanced_framing =
+		(dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
+		1 : 0;
+	printk(BIOS_SPEW, "JZ: %s: alt_reset_cap: %d, only_enh_framing: %d\n", __func__,
+		cfg->alt_scramber_reset_cap, cfg->only_enhanced_framing);
+
+	cfg->lane_count	      = cfg->max_lane_count;
+	cfg->link_bw	      = cfg->max_link_bw;
+	cfg->enhanced_framing = cfg->support_enhanced_framing;
+	return 0;
+}
+
+
+//struct tegra_dc	dc_data = {0};
+struct tegra_dc_sor_data sor_data = {0};
+struct tegra_dc_dp_data	dp_data = {0};
+
+static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp,
+	u8 *rev)
+{
+	u32 size;
+	int ret;
+	u32 status = 0;
+
+	size = 3;
+	ret = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
+		NV_DPCD_REV, rev, &size, &status);
+	if (ret) {
+		printk(BIOS_SPEW,"dp: Failed to read NV_DPCD_REV\n");
+		return ret;
+	}
+	return 0;
+}
+u32 dp_setup_timing(u32 panel_id, u32 width, u32 height);
+void dp_bringup(u32 winb_addr)
+{
+	struct tegra_dc_dp_data	*dp = &dp_data;
+
+	u32	dpcd_rev;
+	u32	pclk_freq;
+//	int	ret;
+
+	printk(BIOS_SPEW, "JZ: %s: entry\n",__func__);
+
+	dp->sor = &sor_data;
+//	dp->sor->dc		= dc;
+	dp->sor->base		= (void *)TEGRA_ARM_SOR;
+//	dp->sor->base_res	= base_res;
+//	dp->sor->sor_clk	= clk;
+	dp->sor->link_cfg	= &dp->link_cfg;
+	dp->sor->portnum	= 0;
+
+	dp->aux_base = (void *)TEGRA_ARM_DPAUX;
+/*	dp->mode = 0;	*/ /* ???? */
+
+	/* read panel info */
+	if (!tegra_dc_dpcd_read_rev(dp, (u8 *)&dpcd_rev)) {
+		printk(BIOS_SPEW,"PANEL info: \n");
+		printk(BIOS_SPEW,"--DPCP version(%#x): %d.%d\n",
+			dpcd_rev, (dpcd_rev >> 4)&0x0f, (dpcd_rev & 0x0f));
+	}
+
+	if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg))
+		printk(BIOS_SPEW,"dp: failed to init link configuration\n");
+
+	dp_link_training((u32)(dp->link_cfg.lane_count),
+			 (u32)(dp->link_cfg.link_bw));
+
+	pclk_freq = dp_setup_timing(5, 2560, 1700); // W: 2560, H: 1700, use_plld2: 1
+	printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n",__func__, pclk_freq);
+
+//	void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr)
+void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr,
+			u32 lane_count, u32 enhanced_framing, u32 panel_edp,
+		     u32 pclkfreq, u32 linkfreq);
+
+	dp_misc_setting(dp->link_cfg.bits_per_pixel,
+			2560, 1700, winb_addr,
+			(u32)dp->link_cfg.lane_count,
+			(u32)dp->link_cfg.enhanced_framing,
+			(u32)dp->link_cfg.alt_scramber_reset_cap,
+			pclk_freq,
+			dp->link_cfg.link_bw * 27);
+
+
+}
+
+void debug_dpaux_print(u32 addr, u32 size)
+{
+	struct tegra_dc_dp_data	*dp = &dp_data;
+	u32 status = 0;
+	u8 buf[16];
+	int i;
+
+	if ((size == 0) || (size > 16)) {
+		printk(BIOS_SPEW,"dp: %s: invalid size %d\n", __func__, size);
+		return;
+	}
+
+	if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
+		addr, buf, &size, &status)) {
+		printk(BIOS_SPEW,"******AuxRead Error: 0x%04x: status 0x%08x\n", addr, status);
+		return;
+	}
+	printk(BIOS_SPEW, "%s: addr: 0x%04x, size: %d\n", __func__, addr, size);
+	for (i=0; i < size; ++i)
+		printk(BIOS_SPEW," %02x", buf[i]);
+
+	printk(BIOS_SPEW,"\n");
+}
+
+int dpaux_read(u32 addr, u32 size, u8 *data)
+{
+
+	struct tegra_dc_dp_data	*dp = &dp_data;
+	u32 status = 0;
+
+	if ((size == 0) || (size > 16)) {
+		printk(BIOS_SPEW,"dp: %s: invalid size %d\n", __func__, size);
+		return -1;
+	}
+
+	if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
+		addr, data, &size, &status)) {
+		printk(BIOS_SPEW,"dp: Failed to read reg %#x, status: %#x\n", addr, status);
+		return -1;
+	}
+
+	return 0;
+}
+
+int dpaux_write(u32 addr, u32 size, u32 data)
+{
+	struct tegra_dc_dp_data	*dp = &dp_data;
+	u32 status = 0;
+	int ret;
+
+	printk(BIOS_SPEW, "JZ: %s: entry, addr: 0x%08x, size: 0x%08x, data: %#x\n",
+		__func__, addr, size, data);
+
+	ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
+		addr, (u8 *)&data, &size, &status);
+	if (ret)
+		printk(BIOS_SPEW,"dp: Failed to write to reg %#x, status: 0x%x\n",
+			addr, status);
+	return ret;
+}
+
diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c
index 06153203b7..4cf6d5f43a 100644
--- a/src/soc/nvidia/tegra/gpio.c
+++ b/src/soc/nvidia/tegra/gpio.c
@@ -36,15 +36,13 @@ void __gpio_input(gpio_t gpio, u32 pull)
 	pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, pinmux_config);
 }
 
-void gpio_output(gpio_t gpio, int value)
+void __gpio_output(gpio_t gpio, int value, u32 od)
 {
-	/* TODO: Set OPEN_DRAIN based on what pin it is? */
-
 	gpio_set_int_enable(gpio, 0);
 	gpio_set_out_value(gpio, value);
 	gpio_set_out_enable(gpio, 1);
 	gpio_set_mode(gpio, GPIO_MODE_GPIO);
-	pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, PINMUX_PULL_NONE);
+	pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, PINMUX_PULL_NONE | od);
 }
 
 enum {
diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h
index 546ea05030..70c1026f44 100644
--- a/src/soc/nvidia/tegra/gpio.h
+++ b/src/soc/nvidia/tegra/gpio.h
@@ -31,10 +31,20 @@ typedef u32 gpio_t;
 #define GPIO(name) ((gpio_t)(GPIO_##name##_INDEX | \
 			     (PINMUX_GPIO_##name << GPIO_PINMUX_SHIFT)))
 
+void __gpio_output(gpio_t gpio, int value, u32 open_drain);
+void __gpio_input(gpio_t gpio, u32 pull);
+
 /* Higher level function wrappers for common GPIO configurations. */
 
-void gpio_output(gpio_t gpio, int value);
-void __gpio_input(gpio_t gpio, u32 pull);
+static inline void gpio_output(gpio_t gpio, int value)
+{
+	__gpio_output(gpio, value, 0);
+}
+
+static inline void gpio_output_open_drain(gpio_t gpio, int value)
+{
+	__gpio_output(gpio, value, PINMUX_OPEN_DRAIN);
+}
 
 static inline void gpio_input(gpio_t gpio)
 {
diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c
new file mode 100644
index 0000000000..0a3434fb0d
--- /dev/null
+++ b/src/soc/nvidia/tegra/usb.c
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <delay.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <soc/clock.h>
+
+#include "usb.h"
+
+/* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */
+void usb_setup_utmip(struct usb_ctlr *usb)
+{
+	/* KHz formulas were guessed from U-Boot constants. Formats unclear. */
+	int khz = clock_get_osc_khz();
+
+	/* Stop UTMI+ crystal clock while we mess with its settings */
+	clrbits_le32(&usb->utmip.misc1, 1 << 30);	/* PHY_XTAL_CLKEN */
+	udelay(1);
+
+	/* Take stuff out of pwrdn and add some magic numbers from U-Boot */
+	write32(0x8 << 25 |		/* HS slew rate [10:4] */
+		0x3 << 22 |		/* HS driver output 'SETUP' [6:4] */
+		0 << 21 |		/* LS bias selection */
+		0 << 18 |		/* PDZI pwrdn */
+		0 << 16 |		/* PD2 pwrdn */
+		0 << 14 |		/* PD pwrdn */
+		1 << 13 |		/* (rst) HS receiver terminations */
+		0x1 << 10 |		/* (rst) LS falling slew rate */
+		0x1 << 8 |		/* (rst) LS rising slew rate */
+		0x4 << 0 |		/* HS driver output 'SETUP' [3:0] */
+		0, &usb->utmip.xcvr0);
+	write32(0x7 << 18 |		/* Termination range adjustment */
+		0 << 4 |		/* PDDR pwrdn */
+		0 << 2 |		/* PDCHRP pwrdn */
+		0 << 0 |		/* PDDISC pwrdn */
+		0, &usb->utmip.xcvr1);
+	write32(1 << 19 |		/* FS send initial J before sync(?) */
+		1 << 16 |		/* (rst) Allow stuff error on SoP */
+		1 << 9 |		/* (rst) Check disc only on EoP */
+		0, &usb->utmip.tx);
+	write32(0x2 << 30 |		/* (rst) Keep pattern on active */
+		1 << 28 |		/* (rst) Realign inertia on pkt */
+		0x1 << 24 |		/* (rst) edges-1 to move sampling */
+		0x3 << 21 |		/* (rst) squelch delay on EoP */
+		0x11 << 15 |		/* cycles until IDLE */
+		0x10 << 10 |		/* elastic input depth */
+		0, &usb->utmip.hsrx0);
+
+	/* U-Boot claims the USBD values for these are used across all UTMI+
+	 * PHYs. That sounds so horribly wrong that I'm not going to implement
+	 * it, but keep it in mind if we're ever not using the USBD port. */
+	write32(0x1 << 24 |		/* HS disconnect detect level [2] */
+		1 << 23 |		/* (rst) IDPD value */
+		1 << 22 |		/* (rst) IDPD select */
+		1 << 11 |		/* (rst) OTG pwrdn */
+		0 << 10 |		/* bias pwrdn */
+		0x1 << 2 |		/* HS disconnect detect level [1:0] */
+		0x2 << 0 |		/* HS squelch detect level */
+		0, &usb->utmip.bias0);
+
+	write32(khz / 2200 << 3 |	/* bias pwrdn cycles (20us?) */
+		1 << 2 |		/* (rst) VBUS wakeup pwrdn */
+		0 << 0 |		/* PDTRK pwrdn */
+		0, &usb->utmip.bias1);
+
+	write32(0xffff << 16 |		/* (rst) */
+		25 * khz / 10 << 0 |	/* TODO: what's this, really? */
+		0, &usb->utmip.debounce);
+
+	udelay(1);
+	setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */
+
+	write32(1 << 12 |		/* UTMI+ enable */
+		0 << 11 |		/* UTMI+ reset */
+		0, &usb->suspend_ctrl);
+}
+
+/*
+ * Tegra EHCI controllers need their usb_mode and lpm_ctrl registers initialized
+ * after every EHCI reset and before any other actions (such as Run/Stop bit)
+ * are taken. We reset the controller here, set those registers and rely on the
+ * fact that libpayload doesn't reset EHCI controllers on initialization for
+ * whatever weird reason. This is ugly, fragile, and I really don't like it, but
+ * making this work will require an ugly hack one way or another so we might as
+ * well take the path of least resistance for now.
+ */
+void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type)
+{
+	int timeout = 1000;
+
+	write32(1 << 1, &usb->ehci_usbcmd);	/* Host Controller Reset */
+	/* TODO: Resets are long, find way to parallelize... or just use XHCI */
+	while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1))
+		/* wait for HC to reset */;
+
+	if (!timeout) {
+		printk(BIOS_ERR, "ERROR: EHCI(%p) reset timeout", usb);
+		return;
+	}
+
+	write32(3 << 0, &usb->usb_mode);	/* Controller mode: HOST */
+	write32(type << 29, &usb->lpm_ctrl);	/* Parallel transceiver selct */
+}
diff --git a/src/soc/nvidia/tegra/usb.h b/src/soc/nvidia/tegra/usb.h
new file mode 100644
index 0000000000..059a815317
--- /dev/null
+++ b/src/soc/nvidia/tegra/usb.h
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA_USB_H__
+#define __SOC_NVIDIA_TEGRA_USB_H__
+
+#include <stdint.h>
+
+struct utmip_ctlr {
+	u32 pll0;
+	u32 pll1;
+	u32 xcvr0;
+	u32 bias0;
+	u32 hsrx0;
+	u32 hsrx1;
+	u32 fslsrx0;
+	u32 fslsrx1;
+	u32 tx;
+	u32 misc0;
+	u32 misc1;
+	u32 debounce;
+	u32 batchrgr;
+	u32 spare;
+	u32 xcvr1;
+	u32 bias1;
+	u32 bias_sts;
+	u32 chrgr_debounce;
+	u32 misc_sts;
+	u32 pmc_wakeup;
+};
+
+struct usb_ctlr {
+	u32 id;
+	u32 _rsv0;
+	u32 host;
+	u32 device;
+	u32 txbuf;			/* 0x010 */
+	u32 rxbuf;
+	u32 _rsv1[58];
+	u16 ehci_caplen;		/* 0x100 */
+	u16 ehci_version;
+	u32 ehci_hcsp;
+	u32 ehci_hccp;
+	u32 _rsv2[5];
+	u32 dci_version;		/* 0x120 */
+	u32 dcc_params;
+	u32 extsts;
+	u32 extintr;
+	u32 ehci_usbcmd;		/* 0x130 */
+	u32 ehci_usbsts;
+	u32 ehci_usbintr;
+	u32 ehci_frindex;
+	u32 _rsv3;			/* 0x140 */
+	u32 ehci_periodic_base;
+	u32 ehci_async_base;
+	u32 async_ttsts;
+	u32 burst_size;			/* 0x150 */
+	u32 tx_fill_tuning;
+	u32 _rsv4;
+	u32 icusb_ctrl;
+	u32 ulpi_viewport;		/* 0x160 */
+	u32 _rsv5[4];
+	u32 ehci_portsc;
+	u32 _rsv6[15];
+	u32 lpm_ctrl;
+	u32 _rsv7[15];
+	u32 otgsc;
+	u32 usb_mode;
+	u32 _rsv8;
+	u32 ep_nak;			/* 0x200 */
+	u32 ep_nak_enable;
+	u32 ep_setup;
+	u32 ep_init;
+	u32 ep_deinit;
+	u32 ep_sts;
+	u32 ep_complete;
+	u32 ep_ctrl[16];
+	u32 _rsv9[105];
+	u32 suspend_ctrl;		/* 0x400 */
+	u32 vbus_sensors;
+	u32 vbus_wakeup_id;
+	u32 alt_vbus_sts;
+	u32 legacy_ctrl;
+	u32 _rsv10[3];
+	u32 interpacket_delay;
+	u32 _rsv11[27];
+	u32 resume_delay;
+	u32 _rsv12;
+	u32 spare;
+	u32 _rsv13[9];
+	u32 new_ctrl;
+	u32 _rsv14[207];
+	struct utmip_ctlr utmip;	/* 0x800 */
+};
+
+enum usb_phy_type {		/* For use in lpm_ctrl[31:29] */
+	USB_PHY_UTMIP = 0,
+	USB_PHY_ULPI = 2,
+	USB_PHY_ICUSB_SER = 3,
+	USB_PHY_HSIC = 4,
+};
+
+void usb_setup_utmip(struct usb_ctlr *usb);
+void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type);
+#endif