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authorElyes HAOUAS <ehaouas@noos.fr>2018-11-26 22:53:49 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-29 12:17:45 +0000
commit6df3b64c77a868ab8526b980561ed2be3fe392b6 (patch)
treea95ac78c1e4e222971ee9749e9e114494681e9c4 /src/soc/nvidia/tegra210
parent1a5ce95815210032783d01e830390ee5b6a54dc5 (diff)
src: Remove duplicated round up function
This removes CEIL_DIV and div_round_up() altogether and replace it by DIV_ROUND_UP defined in commonlib/helpers.h. Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/nvidia/tegra210')
-rw-r--r--src/soc/nvidia/tegra210/clock.c4
-rw-r--r--src/soc/nvidia/tegra210/include/soc/clock.h5
2 files changed, 5 insertions, 4 deletions
diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c
index 6ce2ba1291..5484d62b38 100644
--- a/src/soc/nvidia/tegra210/clock.c
+++ b/src/soc/nvidia/tegra210/clock.c
@@ -330,7 +330,7 @@ static void init_utmip_pll(void)
/* CFG1 */
u32 pllu_enb_ct = 0;
- u32 phy_stb_ct = div_round_up(khz, 300); /* phy_stb_ct = 128 */
+ u32 phy_stb_ct = DIV_ROUND_UP(khz, 300); /* phy_stb_ct = 128 */
write32(CLK_RST_REG(utmip_pll_cfg1),
pllu_enb_ct << UTMIP_CFG1_PLLU_ENABLE_DLY_COUNT_SHIFT |
UTMIP_CFG1_FORCE_PLLU_POWERDOWN_ENABLE |
@@ -341,7 +341,7 @@ static void init_utmip_pll(void)
/* CFG2 */
u32 pllu_stb_ct = 0;
- u32 phy_act_ct = div_round_up(khz, 6400); /* phy_act_ct = 6 */
+ u32 phy_act_ct = DIV_ROUND_UP(khz, 6400); /* phy_act_ct = 6 */
write32(CLK_RST_REG(utmip_pll_cfg2),
phy_act_ct << UTMIP_CFG2_PLL_ACTIVE_DLY_COUNT_SHIFT |
pllu_stb_ct << UTMIP_CFG2_PLLU_STABLE_COUNT_SHIFT |
diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h
index 50d72603ee..87d0850c7a 100644
--- a/src/soc/nvidia/tegra210/include/soc/clock.h
+++ b/src/soc/nvidia/tegra210/include/soc/clock.h
@@ -289,7 +289,7 @@ enum {
* and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you
* will assign this to a u8, it gets nicely truncated for you.
*/
-#define CLK_DIVIDER(REF, FREQ) (div_round_up(((REF) * 2), (FREQ)) - 2)
+#define CLK_DIVIDER(REF, FREQ) (DIV_ROUND_UP(((REF) * 2), (FREQ)) - 2)
/* Calculate clock frequency value from reference and clock divider value
* The discussion in the book is pretty lacking.
@@ -324,7 +324,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
src << CLK_SOURCE_SHIFT | div);
}
-#define get_i2c_clk_div(src,freq) (div_round_up(src, (freq) * (0x19 + 1) * 8) - 1)
+#define get_i2c_clk_div(src, freq) \
+ (DIV_ROUND_UP(src, (freq) * (0x19 + 1) * 8) - 1)
#define get_clk_div(src,freq) CLK_DIVIDER(src,freq)
#define CLK_DIV_MASK 0xff
#define CLK_DIV_MASK_I2C 0xffff