src/soc: Use "foo *bar" instead of "foo* bar"

Change-Id: I21680354f33916b7b4d913f51a842b5d6c2ecef3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

7 files changed, 12 insertions, 12 deletions

diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c
index 51cfc8b2c8..6ce2ba1291 100644
--- a/src/soc/nvidia/tegra210/clock.c
+++ b/src/soc/nvidia/tegra210/clock.c
@@ -654,7 +654,7 @@ void clock_grp_enable_clear_reset(u32 val, u32 *clk_enb_set_reg,
 	write32(rst_dev_clr_reg, val);
 }
 
-static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = {
+static u32 *const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = {
 	CLK_RST_REG(clk_enb_l_set),
 	CLK_RST_REG(clk_enb_h_set),
 	CLK_RST_REG(clk_enb_u_set),
@@ -664,7 +664,7 @@ static u32 * const clk_enb_set_arr[DEV_CONFIG_BLOCKS] = {
 	CLK_RST_REG(clk_enb_y_set),
 };
 
-static u32 * const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = {
+static u32 *const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = {
 	CLK_RST_REG(clk_enb_l_clr),
 	CLK_RST_REG(clk_enb_h_clr),
 	CLK_RST_REG(clk_enb_u_clr),
@@ -674,7 +674,7 @@ static u32 * const clk_enb_clr_arr[DEV_CONFIG_BLOCKS] = {
 	CLK_RST_REG(clk_enb_y_clr),
 };
 
-static u32 * const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = {
+static u32 *const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = {
 	CLK_RST_REG(rst_dev_l_set),
 	CLK_RST_REG(rst_dev_h_set),
 	CLK_RST_REG(rst_dev_u_set),
@@ -684,7 +684,7 @@ static u32 * const rst_dev_set_arr[DEV_CONFIG_BLOCKS] = {
 	CLK_RST_REG(rst_dev_y_set),
 };
 
-static u32 * const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = {
+static u32 *const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = {
 	CLK_RST_REG(rst_dev_l_clr),
 	CLK_RST_REG(rst_dev_h_clr),
 	CLK_RST_REG(rst_dev_u_clr),
@@ -694,7 +694,7 @@ static u32 * const rst_dev_clr_arr[DEV_CONFIG_BLOCKS] = {
 	CLK_RST_REG(rst_dev_y_clr),
 };
 
-static void clock_write_regs(u32 * const regs[DEV_CONFIG_BLOCKS],
+static void clock_write_regs(u32 *const regs[DEV_CONFIG_BLOCKS],
 			     u32 bits[DEV_CONFIG_BLOCKS])
 {
 	int i = 0;
diff --git a/src/soc/nvidia/tegra210/dc.c b/src/soc/nvidia/tegra210/dc.c
index b54614f2fe..b892c602b3 100644
--- a/src/soc/nvidia/tegra210/dc.c
+++ b/src/soc/nvidia/tegra210/dc.c
@@ -23,7 +23,7 @@
 #include <soc/display.h>
 
 int dump = 0;
-unsigned long READL(void * p)
+unsigned long READL(void *p)
 {
         unsigned long value;
 
@@ -40,7 +40,7 @@ unsigned long READL(void * p)
         return value;
 }
 
-void WRITEL(unsigned long value, void * p)
+void WRITEL(unsigned long value, void *p)
 {
         if (dump)
 		printk(BIOS_SPEW, "writel %p %08lx\n", p, value);
diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c
index 5a9d5a513d..532ffc3122 100644
--- a/src/soc/nvidia/tegra210/dsi.c
+++ b/src/soc/nvidia/tegra210/dsi.c
@@ -569,7 +569,7 @@ static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
 	return tegra_mipi_calibrate(dsi->mipi);
 }
 
-static const char * const error_report[16] = {
+static const char *const error_report[16] = {
 	"SoT Error",
 	"SoT Sync Error",
 	"EoT Sync Error",
diff --git a/src/soc/nvidia/tegra210/flow_ctrl.c b/src/soc/nvidia/tegra210/flow_ctrl.c
index ea5b2795b3..0eb835788a 100644
--- a/src/soc/nvidia/tegra210/flow_ctrl.c
+++ b/src/soc/nvidia/tegra210/flow_ctrl.c
@@ -36,7 +36,7 @@
 #define FLOW_CTRL_CPU1_CSR		0x18
 #define FLOW_CTRL_CC4_CORE0_CTRL	0x6c
 
-static void *tegra_flowctrl_base = (void*)TEGRA_FLOW_BASE;
+static void *tegra_flowctrl_base = (void *)TEGRA_FLOW_BASE;
 
 static const uint8_t flowctrl_offset_halt_cpu[] = {
 	FLOW_CTRL_HALT_CPU0_EVENTS,
diff --git a/src/soc/nvidia/tegra210/include/soc/id.h b/src/soc/nvidia/tegra210/include/soc/id.h
index 0903ba98ef..42b2be6535 100644
--- a/src/soc/nvidia/tegra210/include/soc/id.h
+++ b/src/soc/nvidia/tegra210/include/soc/id.h
@@ -23,7 +23,7 @@
 static inline int context_avp(void)
 {
 	const uint32_t avp_id = 0xaaaaaaaa;
-	void * const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE;
+	void *const uptag = (void *)(uintptr_t)TEGRA_PG_UP_BASE;
 
 	return read32(uptag) == avp_id;
 }
diff --git a/src/soc/nvidia/tegra210/mtc.c b/src/soc/nvidia/tegra210/mtc.c
index f71e5e8f85..97eb3dee14 100644
--- a/src/soc/nvidia/tegra210/mtc.c
+++ b/src/soc/nvidia/tegra210/mtc.c
@@ -31,7 +31,7 @@ int tegra210_run_mtc(void)
 	struct region_device fh;
 	struct cbfsf mtc_file;
 
-	void * const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS;
+	void *const mtc = (void *)(uintptr_t)CONFIG_MTC_ADDRESS;
 	void *dvfs_table;
 	size_t (*mtc_fw)(void **dvfs_table) = (void *)mtc;
 
diff --git a/src/soc/nvidia/tegra210/power.c b/src/soc/nvidia/tegra210/power.c
index 6b22f5a935..cef5b99b5c 100644
--- a/src/soc/nvidia/tegra210/power.c
+++ b/src/soc/nvidia/tegra210/power.c
@@ -36,7 +36,7 @@ static int partition_powered(int id)
 	return POWER_GATE;
 }
 
-static const char * const power_gate_string[] = {
+static const char *const power_gate_string[] = {
 	[POWER_GATE] = "Gat",
 	[POWER_UNGATE] = "Ungat",
 };