arm64: remove secmon

It's been decided to only support ARM Trusted Firmware for
any EL3 monitor. That means any SoC that requires PSCI
needs to add its support for ATF otherwise multi-processor
bring up won't work.

Change-Id: Ic931dbf5eff8765f4964374910123a197148f0ff
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11897
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>

1 files changed, 0 insertions, 46 deletions

diff --git a/src/soc/nvidia/tegra210/secmon.c b/src/soc/nvidia/tegra210/secmon.c
deleted file mode 100644
index 392e06c71b..0000000000
--- a/src/soc/nvidia/tegra210/secmon.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/secmon.h>
-#include <console/console.h>
-#include <soc/addressmap.h>
-#include <soc/mmu_operations.h>
-
-static void soc_get_secure_mem(uint64_t *base, size_t *size)
-{
-	uintptr_t tz_base_mib;
-	size_t tz_size_mib;
-
-	carveout_range(CARVEOUT_TZ, &tz_base_mib, &tz_size_mib);
-
-	tz_base_mib *= MiB;
-	tz_size_mib *= MiB;
-
-	*base = tz_base_mib;
-	*size = tz_size_mib;
-}
-
-void soc_get_secmon_base_size(uint64_t *base, size_t *size)
-{
-	uintptr_t tz_base;
-	size_t ttb_size, tz_size;
-
-	soc_get_secure_mem(&tz_base, &tz_size);
-
-	ttb_size = CONFIG_TTB_SIZE_MB * MiB;
-
-	*base = tz_base + ttb_size;
-	*size = tz_size - ttb_size;
-}