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| author | Maulik V Vaghela <maulik.v.vaghela@intel.com> | 2021-02-23 14:06:01 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-12 00:51:11 +0000 |
| commit | 01ecb77ef64c8fdce5258dc75b7c4eaf1ed57cd0 (patch) | |
| tree | 7efc7ee8a38d4879cc28d9be443195c2b0b08b69 /src/soc/nvidia/tegra210/sdram_lp0.c | |
| parent | d1bf408da8f0dde7f5f5c29aedd9ee57069311c1 (diff) | |
mb/intel/adlrvp: Fill CmdMirror and DqDqsRetraining for ADLRVP
ADL-M LP4 RVP has command mirror enabled and we need to fill correct
value of this UPD to pass the MRC.
Also, Value of TxDqDqsRetraining is set to 1 by default and we need to
disable it for only ADL-M LP5 RVP.
BUG=None
BRANCH=None
TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board
Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/sdram_lp0.c')
0 files changed, 0 insertions, 0 deletions