diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2020-06-05 09:51:30 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-08 19:08:03 +0000 |
| commit | e80a1b1690d9d70e14cd7aa0b99fa317ac33b4e4 (patch) | |
| tree | 6c85666cdbbcd5701de823666d8d00a2903a0475 /src/soc/nvidia/tegra210/ram_code.c | |
| parent | d6161d46ff9563154f5c46509c0498ed11b16607 (diff) | |
soc/amd/picasso: remove save/restore MTRRs around FSP-M
AGESA FSP-M implementation is now not updating MTRRs out from
under the caller. As such, remove the save/restore of MTRRs
from the FSP-M call.
BUG=b:155426691
Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/nvidia/tegra210/ram_code.c')
0 files changed, 0 insertions, 0 deletions