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| author | Hannah Williams <hannah.williams@intel.com> | 2015-05-13 21:48:52 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-28 20:35:59 +0100 |
| commit | 26f64069d26fd23a30d85c3128ce748ebdff5fcd (patch) | |
| tree | 6840ce7d4e7350d74f47696bdb209e4014a3a49e /src/soc/nvidia/tegra210/ram_code.c | |
| parent | c68163811680caf998e85a5005065183aa1a80a7 (diff) | |
soc/braswell: Configure Boot Flash Write Protect status GPIO
Set up the GPIO(MF_ISH_GPIO_4) to read WP status.
TEST=Use crossystem to read the WP status
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I17cbcba013e2a11c2527731df985aa1243065eff
Original-Reviewed-on: https://chromium-review.googlesource.com/302424
Original-Tested-by: John Zhao <john.zhao@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13185
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/nvidia/tegra210/ram_code.c')
0 files changed, 0 insertions, 0 deletions