diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:44:36 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-22 17:14:59 +0000 |
| commit | 555c3b1d9b05033be0e49ec62fba43536efd410f (patch) | |
| tree | 64b1822fae347bf71c98d9ad48ca55c602bc04a7 /src/soc/nvidia/tegra210/lp0 | |
| parent | cb795f0ff96f59a1a667f83143d855c463eff5ca (diff) | |
soc/nvidia: Drop unneeded empty lines
Change-Id: I76430f5cd4b661aff85e2d21722f41c03362b1bd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44598
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/lp0')
| -rw-r--r-- | src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 0740d36807..9e2754d05f 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -26,7 +26,6 @@ enum { UP_TAG_AVP = 0xaaaaaaaa }; - /* APB Misc JTAG Configuration Register */ static uint32_t *misc_pp_config_ctl_ptr = (void *)(APB_MISC_BASE + 0x24); enum { @@ -40,7 +39,6 @@ enum { CFG2TMC_RAM_SVOP_PDP_VAL_2 = 0x2 << 24, }; - /* PINMUX registers. */ static uint32_t *pinmux_pwr_i2c_scl_ptr = (void *)(PINMUX_BASE + 0xdc); static uint32_t *pinmux_pwr_i2c_sda_ptr = (void *)(PINMUX_BASE + 0xe0); @@ -57,7 +55,6 @@ enum { static uint32_t *timer_us_ptr = (void *)(TIMER_BASE + 0x10); static uint32_t *timer_us_cfg_ptr = (void *)(TIMER_BASE + 0x14); - /* Clock and reset controller registers. */ static uint32_t *clk_rst_rst_devices_l_ptr = (void *)(CLK_RST_BASE + 0x4); enum { @@ -264,7 +261,6 @@ enum { ACTIVE_SLOW = 0x1 << 0 }; - /* Power management controller registers. */ enum { PARTID_CRAIL = 0, @@ -346,7 +342,6 @@ enum { static uint32_t *sb_aa64_reset_low = (void *)(SECURE_BOOT_BASE + 0x30); static uint32_t *sb_aa64_reset_high = (void *)(SECURE_BOOT_BASE + 0x34); - /* EMC registers */ static uint32_t *pmacro_cfg_pm_global = (void *)(EMC_BASE + 0xc30); enum { @@ -408,7 +403,6 @@ enum { #define MAX77621_VOUT_VAL (0x80 | 0x27) #define MAX77621_VOUT_DATA (MAX77621_VOUT_REG | (MAX77621_VOUT_VAL << 8)) - /* Utility functions. */ static __always_inline void __noreturn halt(void) @@ -592,7 +586,6 @@ static void enable_select_cpu_clocks(void) udelay(10); } - /* Function unit configuration. */ static void config_core_sight(void) @@ -609,7 +602,6 @@ static void config_core_sight(void) write32(clk_rst_rst_dev_u_clr_ptr, SWR_CSITE_RST); } - /* RAM repair */ void ram_repair(void) @@ -621,7 +613,6 @@ void ram_repair(void) ; } - /* Power. */ static void power_on_partition(unsigned int id) @@ -764,7 +755,6 @@ static void mbist_workaround(void) write32(clk_rst_lvl2_clk_gate_ovrd_ptr, 0x01000000); /* QSPI OVR=1 */ write32(clk_rst_lvl2_clk_gate_ovre_ptr, 0x00000c00); - clks_to_be_cleared = read32(clk_rst_clk_out_enb_l_ptr); clks_to_be_cleared &= ~MBIST_CLK_ENB_L_0; write32(clk_rst_clk_enb_l_clr_ptr, clks_to_be_cleared); @@ -1085,7 +1075,6 @@ void lp0_resume(void) FLOW_MODE_STOP | EVENT_JTAG); } - /* Header. */ extern uint8_t blob_data; |