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authorPatrick Georgi <pgeorgi@chromium.org>2015-06-22 19:41:29 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-06-30 21:43:01 +0200
commit40a3e321d4e8f2877de1700db67b8c7f7ea89820 (patch)
treeb8270b2ceb9e290d2e4e9a99868acb9cd335de6f /src/soc/nvidia/tegra210/jdi_25x18_display
parent7f641e68f25c0b79960a97a6b265851c46298aae (diff)
nvidia/tegra210: add new SoC
This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I81853434600390d643160fe57554495b2bfe60ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/jdi_25x18_display')
-rw-r--r--src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c215
-rw-r--r--src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h131
2 files changed, 346 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c
new file mode 100644
index 0000000000..2149ca936e
--- /dev/null
+++ b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c
@@ -0,0 +1,215 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <lib.h>
+#include <stdlib.h>
+#include <delay.h>
+#include <soc/addressmap.h>
+#include <soc/clock.h>
+#include <device/device.h>
+#include <soc/nvidia/tegra/types.h>
+#include "../chip.h"
+#include <soc/display.h>
+#include <soc/mipi_dsi.h>
+#include <soc/tegra_dsi.h>
+#include "panel-jdi-lpm102a188a.h"
+
+struct panel_jdi jdi_data[NUM_DSI];
+
+int panel_jdi_prepare(struct panel_jdi *jdi)
+{
+ int ret;
+ u8 data;
+
+ if (jdi->enabled)
+ return 0;
+
+ ret = mipi_dsi_dcs_set_column_address(jdi->dsi, 0,
+ jdi->mode->xres / 2 - 1); // 2560/2
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set column address: %d\n", ret);
+
+ ret = mipi_dsi_dcs_set_column_address(jdi->dsi->slave, 0,
+ jdi->mode->xres / 2 - 1);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set column address: %d\n", ret);
+
+ ret = mipi_dsi_dcs_set_page_address(jdi->dsi, 0,
+ jdi->mode->yres - 1);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set page address: %d\n", ret);
+
+ ret = mipi_dsi_dcs_set_page_address(jdi->dsi->slave, 0,
+ jdi->mode->yres - 1);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set page address: %d\n", ret);
+
+ ret = mipi_dsi_dcs_set_tear_on(jdi->dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set tear on: %d\n", ret);
+
+ ret = mipi_dsi_dcs_set_tear_on(jdi->dsi->slave,
+ MIPI_DSI_DCS_TEAR_MODE_VBLANK);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set tear on: %d\n", ret);
+
+ ret = mipi_dsi_dcs_set_address_mode(jdi->dsi, false, false, false,
+ false, false, false, false, false);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set address mode: %d\n", ret);
+
+ ret = mipi_dsi_dcs_set_address_mode(jdi->dsi->slave, false, false,
+ false, false, false, false, false, false);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set address mode: %d\n", ret);
+
+ ret = mipi_dsi_dcs_set_pixel_format(jdi->dsi, 0x77);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set pixel format: %d\n", ret);
+
+ ret = mipi_dsi_dcs_set_pixel_format(jdi->dsi->slave, 0x77);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set pixel format: %d\n", ret);
+
+ data = 0xFF;
+ ret = mipi_dsi_dcs_write(jdi->dsi, 0x51, &data, 1);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set 0x51: %d\n", ret);
+
+ data = 0xFF;
+ ret = mipi_dsi_dcs_write(jdi->dsi->slave, 0x51, &data, 1);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set 0x51: %d\n", ret);
+
+ data = 0x24;
+ ret = mipi_dsi_dcs_write(jdi->dsi, 0x53, &data, 1);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set 0x53: %d\n", ret);
+
+ data = 0x24;
+ ret = mipi_dsi_dcs_write(jdi->dsi->slave, 0x53, &data, 1);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set 0x53: %d\n", ret);
+
+ data = 0x00;
+ ret = mipi_dsi_dcs_write(jdi->dsi, 0x55, &data, 1);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set 0x55: %d\n", ret);
+
+ data = 0x00;
+ ret = mipi_dsi_dcs_write(jdi->dsi->slave, 0x55, &data, 1);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set 0x55: %d\n", ret);
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(jdi->dsi);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to exit sleep mode: %d\n", ret);
+
+ ret = mipi_dsi_dcs_exit_sleep_mode(jdi->dsi->slave);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to exit sleep mode: %d\n", ret);
+ mdelay(150);
+
+ ret = mipi_dsi_dcs_set_display_on(jdi->dsi);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set display on: %d\n", ret);
+
+ ret = mipi_dsi_dcs_set_display_on(jdi->dsi->slave);
+ if (ret < 0)
+ printk(BIOS_ERR, "failed to set display on: %d\n", ret);
+ mdelay(50);
+
+ jdi->enabled = true;
+
+ return 0;
+}
+
+static int panel_jdi_enslave(struct mipi_dsi_device *master,
+ struct mipi_dsi_device *slave)
+{
+ int ret;
+
+ ret = mipi_dsi_attach(master);
+ if (ret < 0)
+ return ret;
+
+ return ret;
+}
+
+static int panel_jdi_liberate(struct mipi_dsi_device *master,
+ struct mipi_dsi_device *slave)
+{
+ int ret;
+
+ ret = mipi_dsi_detach(master);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static const struct mipi_dsi_master_ops panel_jdi_master_ops = {
+ .enslave = panel_jdi_enslave,
+ .liberate = panel_jdi_liberate,
+};
+
+struct panel_jdi *panel_jdi_dsi_probe(struct mipi_dsi_device *dsi)
+{
+ static int index = 0;
+ struct panel_jdi *jdi;
+ int ret;
+
+ if (index >= NUM_DSI)
+ return (void *)-EPTR;
+
+ jdi = &jdi_data[index++];
+
+ jdi->dsi = dsi;
+
+ dsi->lanes = 4;
+ dsi->format = MIPI_DSI_FMT_RGB888;
+ dsi->mode_flags = 0;
+
+ if (dsi->master) {
+ ret = mipi_dsi_attach(dsi);
+ if (ret < 0) {
+ printk(BIOS_ERR, "mipi_dsi_attach() failed: %d\n", ret);
+ return (void *)-EPTR;
+ }
+
+ ret = mipi_dsi_enslave(dsi->master, dsi);
+ if (ret < 0) {
+ printk(BIOS_ERR, "mipi_dsi_enslave() failed: %d\n",
+ ret);
+ return (void *)-EPTR;
+ }
+
+ return jdi;
+ }
+
+ dsi->ops = &panel_jdi_master_ops;
+
+ jdi->enabled = 0;
+ jdi->width_mm = 211;
+ jdi->height_mm = 148;
+
+ return jdi;
+}
diff --git a/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h
new file mode 100644
index 0000000000..b345971060
--- /dev/null
+++ b/src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.h
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+#ifndef _PANEL_JDI_LPM102A188A_H_
+#define _PANEL_JDI_LPM102A188A_H_
+
+#define LP8557_MAX_BRIGHTNESS 0xFFF;
+
+#define LP8557_COMMAND 0x00
+#define LP8557_COMMAND_ON (1 << 0)
+
+#define LP8557_BRIGHTNESS_LOW 0x03
+#define LP8557_BRIGHTNESS_LOW_MASK(x) (((x) & 0xF) << 4)
+
+#define LP8557_BRIGHTNESS_HIGH 0x04
+#define LP8557_BRIGHTNESS_HIGH_MASK(x) (((x) & 0xFF0) >> 4)
+
+enum lp8557_config_brightness_mode {
+ LP8557_CONFIG_BRTMODE_PWM = 0x0,
+ LP8557_CONFIG_BRTMODE_REG,
+ LP8557_CONFIG_BRTMODE_PWM_REG_SHAPE_PWM,
+ LP8557_CONFIG_BRTMODE_PWM_REG_SHAPE_BRIGHTNESS,
+ LP8557_CONFIG_BRTMODE_MAX,
+};
+#define LP8557_CONFIG 0x10
+#define LP8557_CONFIG_BRTMODE(x) (((x) & 0x3) << 0)
+#define LP8557_CONFIG_AUTO_DETECT_LED (1 << 2)
+#define LP8557_CONFIG_PWM_STANDBY (1 << 7)
+
+enum lp8557_current {
+ LP8557_CURRENT_5_MA = 0x0,
+ LP8557_CURRENT_10_MA,
+ LP8557_CURRENT_13_MA,
+ LP8557_CURRENT_15_MA,
+ LP8557_CURRENT_18_MA,
+ LP8557_CURRENT_20_MA,
+ LP8557_CURRENT_23_MA,
+ LP8557_CURRENT_25_MA,
+ LP8557_CURRENT_MAX,
+};
+#define LP8557_CURRENT 0x11
+#define LP8557_CURRENT_MAXCURR(x) (((x) & 0x7) << 0)
+#define LP8557_CURRENT_ISET (1 << 7)
+
+enum lp8557_pgen_frequency {
+ LP8557_PGEN_FREQ_4_9_KHZ = 0x0,
+ LP8557_PGEN_FREQ_9_8_KHZ,
+ LP8557_PGEN_FREQ_14_6_KHZ,
+ LP8557_PGEN_FREQ_19_5_KHZ,
+ LP8557_PGEN_FREQ_24_4_KHZ,
+ LP8557_PGEN_FREQ_29_3_KHZ,
+ LP8557_PGEN_FREQ_34_2_KHZ,
+ LP8557_PGEN_FREQ_39_1_KHZ,
+ LP8557_PGEN_FREQ_MAX,
+};
+#define LP8557_PGEN 0x12
+#define LP8557_PGEN_FREQ(x) (((x) & 0x7) << 0)
+#define LP8557_PGEN_MAGIC (5 << 3)
+#define LP8557_PGEN_FSET (1 << 7)
+
+enum lp8557_boost_freq {
+ LP8557_BOOST_FREQ_500_KHZ = 0x0,
+ LP8557_BOOST_FREQ_1_MHZ,
+ LP8557_BOOST_FREQ_MAX,
+};
+enum lp8557_boost_bcomp {
+ LP8557_BOOST_BCOMP_OPTION_0 = 0x0,
+ LP8557_BOOST_BCOMP_OPTION_1,
+ LP8557_BOOST_BCOMP_MAX,
+};
+#define LP8557_BOOST 0x13
+#define LP8557_BOOST_FREQ(x) (((x) & 0x1) << 0)
+#define LP8557_BOOST_BCOMP(x) (((x) & 0x1) << 1)
+#define LP8557_BOOST_BCSET (1 << 6)
+#define LP8557_BOOST_BFSET (1 << 7)
+
+#define LP8557_LED_ENABLE 0x14
+#define LP8557_LED_ENABLE_SINKS(x) (((x) & 0x3F) << 0)
+#define LP8557_LED_ENABLE_MAGIC (2 << 6)
+
+enum lp8557_step_ramp {
+ LP8557_STEP_RAMP_0_MS = 0x0,
+ LP8557_STEP_RAMP_50_MS,
+ LP8557_STEP_RAMP_100_MS,
+ LP8557_STEP_RAMP_200_MS,
+ LP8557_STEP_RAMP_MAX,
+};
+enum lp8557_step_smoothing {
+ LP8557_STEP_SMOOTHING_NONE = 0x0,
+ LP8557_STEP_SMOOTHING_LIGHT,
+ LP8557_STEP_SMOOTHING_MEDIUM,
+ LP8557_STEP_SMOOTHING_HEAVY,
+ LP8557_STEP_SMOOTHING_MAX,
+};
+#define LP8557_STEP 0x15
+#define LP8557_STEP_RAMP(x) (((x) & 0x3) << 0)
+#define LP8557_STEP_SMOOTHING(x) (((x) & 0x3) << 6)
+
+struct mipi_dsi_device;
+struct soc_nvidia_tegra210_config;
+
+struct panel_jdi {
+ struct mipi_dsi_device *dsi;
+ const struct soc_nvidia_tegra210_config *mode;
+
+ /* Physical size */
+ unsigned int width_mm;
+ unsigned int height_mm;
+
+ int enabled;
+};
+
+struct panel_jdi *panel_jdi_dsi_probe(struct mipi_dsi_device *dsi);
+int panel_jdi_prepare(struct panel_jdi *jdi);
+
+#endif