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authorDeepti Deshatty <deepti.deshatty@intel.com>2021-05-12 17:45:37 +0530
committerPatrick Georgi <pgeorgi@google.com>2021-05-18 10:09:04 +0000
commit8e7facf3437d633af747f6163cd66525ea14860e (patch)
treec361c457b54cabb04f430bf6def72fad6e9aa7e0 /src/soc/nvidia/tegra210/gic.c
parentd5433afb28ad6e9c3435310032ed8c7415d1875f (diff)
soc/intel/alderlake: mb/intel/sm: Add tcss code
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/nvidia/tegra210/gic.c')
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