ryu: display: Split dc functions from dsi display code

dc supporting functions can be used for other than dsi display
interfaces. This change is preparing for supporting sor display
interface.

BUG=chrome-os-partner:34336
BRANCH=none
TEST=build ryu and test dev/rec mode, also build rush ok

Change-Id: I8a310e188fae70d7726c4360894b392c4546e105
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a7ab7225e3419a0fd93894dbb9a959390f29945b
Original-Change-Id: Id14cbd89457cb91c23526927a432f4eb7cc6291b
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/234270
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9583
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

5 files changed, 114 insertions, 118 deletions

diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index fc22b2a69b..9d4c33ddf3 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -66,8 +66,8 @@ ramstage-y += cbmem.c
 ramstage-y += cpu.c
 ramstage-y += cpu_lib.S
 ramstage-y += clock.c
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c
-ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += tegra_dsi.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += dc.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += dsi.c
 ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += mipi_dsi.c
 ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += mipi.c
 ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += mipi-phy.c
diff --git a/src/soc/nvidia/tegra132/chip.h b/src/soc/nvidia/tegra132/chip.h
index 2468870569..fbbef500d4 100644
--- a/src/soc/nvidia/tegra132/chip.h
+++ b/src/soc/nvidia/tegra132/chip.h
@@ -21,6 +21,7 @@
 #define __SOC_NVIDIA_TEGRA132_CHIP_H__
 #include <soc/addressmap.h>
 #include <stdint.h>
+#include <soc/nvidia/tegra/dc.h>
 
 struct soc_nvidia_tegra132_config {
 	/* Address to monitor if spintable employed. */
@@ -68,6 +69,7 @@ struct soc_nvidia_tegra132_config {
 	int refresh;		/* display refresh rate */
 
 	int pixel_clock;	/* dc pixel clock source rate */
+	int win_opt;
 };
 
 #endif /* __SOC_NVIDIA_TEGRA132_CHIP_H__ */
diff --git a/src/soc/nvidia/tegra132/display.c b/src/soc/nvidia/tegra132/dc.c
index d616b7356f..e5ab23ad89 100644
--- a/src/soc/nvidia/tegra132/display.c
+++ b/src/soc/nvidia/tegra132/dc.c
@@ -19,20 +19,9 @@
 #include <console/console.h>
 #include <arch/io.h>
 #include <stdint.h>
-#include <lib.h>
 #include <stdlib.h>
-#include <delay.h>
-#include <soc/addressmap.h>
 #include <device/device.h>
-#include <device/i2c.h>
-#include <string.h>
-#include <cpu/cpu.h>
-#include <boot/tables.h>
-#include <cbmem.h>
-#include <edid.h>
-#include <soc/clock.h>
 #include <soc/nvidia/tegra/dc.h>
-#include <soc/funitcfg.h>
 #include "chip.h"
 #include <soc/display.h>
 
@@ -89,7 +78,7 @@ static void print_mode(const struct soc_nvidia_tegra132_config *config)
 	}
 }
 
-static int update_display_mode(struct display_controller *disp_ctrl,
+int update_display_mode(struct display_controller *disp_ctrl,
 			       struct soc_nvidia_tegra132_config *config)
 {
 	print_mode(config);
@@ -108,8 +97,8 @@ static int update_display_mode(struct display_controller *disp_ctrl,
 	WRITEL(0x0, &disp_ctrl->disp.disp_timing_opt);
 	WRITEL(0x0, &disp_ctrl->disp.disp_color_ctrl);
 
-	// select DSI
-	WRITEL(DSI_ENABLE, &disp_ctrl->disp.disp_win_opt);
+	/* select win opt */
+	WRITEL(config->win_opt, &disp_ctrl->disp.disp_win_opt);
 
 	WRITEL(config->vref_to_sync << 16 | config->href_to_sync,
 		&disp_ctrl->disp.ref_to_sync);
@@ -156,7 +145,7 @@ static int update_display_mode(struct display_controller *disp_ctrl,
  *   display enable register (_DISP_DISP_WIN_OPTIONS). This is
  *   becasue framebuffer is not available until payload stage.
  */
-static void update_window(const struct soc_nvidia_tegra132_config *config)
+void update_window(const struct soc_nvidia_tegra132_config *config)
 {
 	struct display_controller *disp_ctrl =
 			(void *)config->display_controller;
@@ -197,7 +186,7 @@ static void update_window(const struct soc_nvidia_tegra132_config *config)
 	WRITEL(val, &disp_ctrl->cmd.state_ctrl);
 }
 
-static int tegra_dc_init(struct display_controller *disp_ctrl)
+int tegra_dc_init(struct display_controller *disp_ctrl)
 {
 	/* do not accept interrupts during initialization */
 	WRITEL(0x00000000, &disp_ctrl->cmd.int_mask);
@@ -232,98 +221,3 @@ static int tegra_dc_init(struct display_controller *disp_ctrl)
 
 	return 0;
 }
-
-void display_startup(device_t dev)
-{
-	struct soc_nvidia_tegra132_config *config = dev->chip_info;
-	struct display_controller *disp_ctrl =
-			(void *)config->display_controller;
-	u32 plld_rate;
-
-	u32 framebuffer_size_mb = config->framebuffer_size / MiB;
-	u32 framebuffer_base_mb= config->framebuffer_base / MiB;
-
-	printk(BIOS_INFO, "%s: entry: disp_ctrl: %p.\n",
-		 __func__, disp_ctrl);
-
-	if (disp_ctrl == NULL) {
-		printk(BIOS_ERR, "Error: No dc is assigned by dt.\n");
-		return;
-	}
-
-	if (framebuffer_size_mb == 0){
-		framebuffer_size_mb = ALIGN_UP(config->display_xres *
-			config->display_yres *
-			(config->framebuffer_bits_per_pixel / 8), MiB)/MiB;
-	}
-
-	config->framebuffer_size = framebuffer_size_mb * MiB;
-	config->framebuffer_base = framebuffer_base_mb * MiB;
-
-	/*
-	 * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
-	 * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
-	 * update_display_mode() for detail.
-	 */
-	/* set default plld */
-	plld_rate = clock_configure_plld(config->pixel_clock * 2);
-	if (plld_rate == 0) {
-		printk(BIOS_ERR, "dc: clock init failed\n");
-		return;
-	}
-
-	/* set disp1's clock source to PLLD_OUT0 */
-	clock_configure_source(disp1, PLLD, (plld_rate/KHz)/2);
-
-	/* Init dc */
-	if (tegra_dc_init(disp_ctrl)) {
-		printk(BIOS_ERR, "dc: init failed\n");
-		return;
-	}
-
-	/* Configure dc mode */
-	if (update_display_mode(disp_ctrl, config)) {
-		printk(BIOS_ERR, "dc: failed to configure display mode.\n");
-		return;
-	}
-
-	/* Configure and enable dsi controller and panel */
-	if (dsi_enable(config)) {
-		printk(BIOS_ERR, "%s: failed to enable dsi controllers.\n",
-			__func__);
-		return;
-	}
-
-	/* Set up window */
-	update_window(config);
-	printk(BIOS_INFO, "%s: display init done.\n", __func__);
-
-	/*
-	 * Pass panel information to cb tables
-	 */
-	struct edid edid;
-	/* Align bytes_per_line to 64 bytes as required by dc */
-	edid.bytes_per_line = ALIGN_UP((config->display_xres *
-				config->framebuffer_bits_per_pixel / 8), 64);
-	edid.x_resolution = edid.bytes_per_line /
-				(config->framebuffer_bits_per_pixel / 8);
-	edid.y_resolution = config->display_yres;
-	edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel;
-
-	printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n "
-			"               x_res x y_res: %d x %d, size: %d\n",
-			 __func__, edid.bytes_per_line,
-			edid.framebuffer_bits_per_pixel,
-			edid.x_resolution, edid.y_resolution,
-			(edid.bytes_per_line * edid.y_resolution));
-
-	set_vbe_mode_info_valid(&edid, 0);
-
-	/*
-	 * After this point, it is payload's responsibility to allocate
-	 * framebuffer and sets the base address to dc's
-	 * WINBUF_START_ADDR register and enables window by setting dc's
-	 * DISP_DISP_WIN_OPTIONS register.
-	 */
-}
-
diff --git a/src/soc/nvidia/tegra132/tegra_dsi.c b/src/soc/nvidia/tegra132/dsi.c
index f1e7c9f1c6..cfeb7fdebc 100644
--- a/src/soc/nvidia/tegra132/tegra_dsi.c
+++ b/src/soc/nvidia/tegra132/dsi.c
@@ -26,7 +26,9 @@
 #include <soc/addressmap.h>
 #include <soc/clock.h>
 #include <device/device.h>
+#include <edid.h>
 #include <soc/nvidia/tegra/types.h>
+#include <soc/nvidia/tegra/dc.h>
 #include "chip.h"
 #include <soc/display.h>
 #include <soc/mipi_dsi.h>
@@ -845,7 +847,7 @@ static int dsi_probe(struct soc_nvidia_tegra132_config *config)
 	return 0;
 }
 
-int dsi_enable(struct soc_nvidia_tegra132_config *config)
+static int dsi_enable(struct soc_nvidia_tegra132_config *config)
 {
 	struct tegra_dsi *dsi_a = &dsi_data[DSI_A];
 
@@ -872,3 +874,97 @@ int dsi_enable(struct soc_nvidia_tegra132_config *config)
 
 	return 0;
 }
+
+void display_startup(device_t dev)
+{
+	struct soc_nvidia_tegra132_config *config = dev->chip_info;
+	struct display_controller *disp_ctrl =
+			(void *)config->display_controller;
+	u32 plld_rate;
+
+	u32 framebuffer_size_mb = config->framebuffer_size / MiB;
+	u32 framebuffer_base_mb= config->framebuffer_base / MiB;
+
+	printk(BIOS_INFO, "%s: entry: disp_ctrl: %p.\n",
+		 __func__, disp_ctrl);
+
+	if (disp_ctrl == NULL) {
+		printk(BIOS_ERR, "Error: No dc is assigned by dt.\n");
+		return;
+	}
+
+	if (framebuffer_size_mb == 0){
+		framebuffer_size_mb = ALIGN_UP(config->display_xres *
+			config->display_yres *
+			(config->framebuffer_bits_per_pixel / 8), MiB)/MiB;
+	}
+
+	config->framebuffer_size = framebuffer_size_mb * MiB;
+	config->framebuffer_base = framebuffer_base_mb * MiB;
+
+	/*
+	 * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER
+	 * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the
+	 * update_display_mode() for detail.
+	 */
+	/* set default plld */
+	plld_rate = clock_configure_plld(config->pixel_clock * 2);
+	if (plld_rate == 0) {
+		printk(BIOS_ERR, "dc: clock init failed\n");
+		return;
+	}
+
+	/* set disp1's clock source to PLLD_OUT0 */
+	clock_configure_source(disp1, PLLD, (plld_rate/KHz)/2);
+
+	/* Init dc */
+	if (tegra_dc_init(disp_ctrl)) {
+		printk(BIOS_ERR, "dc: init failed\n");
+		return;
+	}
+
+	/* Configure dc mode */
+	if (update_display_mode(disp_ctrl, config)) {
+		printk(BIOS_ERR, "dc: failed to configure display mode.\n");
+		return;
+	}
+
+	/* Configure and enable dsi controller and panel */
+	if (dsi_enable(config)) {
+		printk(BIOS_ERR, "%s: failed to enable dsi controllers.\n",
+			__func__);
+		return;
+	}
+
+	/* Set up window */
+	update_window(config);
+	printk(BIOS_INFO, "%s: display init done.\n", __func__);
+
+	/*
+	 * Pass panel information to cb tables
+	 */
+	struct edid edid;
+	/* Align bytes_per_line to 64 bytes as required by dc */
+	edid.bytes_per_line = ALIGN_UP((config->display_xres *
+				config->framebuffer_bits_per_pixel / 8), 64);
+	edid.x_resolution = edid.bytes_per_line /
+				(config->framebuffer_bits_per_pixel / 8);
+	edid.y_resolution = config->display_yres;
+	edid.framebuffer_bits_per_pixel = config->framebuffer_bits_per_pixel;
+
+	printk(BIOS_INFO, "%s: bytes_per_line: %d, bits_per_pixel: %d\n "
+			"               x_res x y_res: %d x %d, size: %d\n",
+			 __func__, edid.bytes_per_line,
+			edid.framebuffer_bits_per_pixel,
+			edid.x_resolution, edid.y_resolution,
+			(edid.bytes_per_line * edid.y_resolution));
+
+	set_vbe_mode_info_valid(&edid, 0);
+
+	/*
+	 * After this point, it is payload's responsibility to allocate
+	 * framebuffer and sets the base address to dc's
+	 * WINBUF_START_ADDR register and enables window by setting dc's
+	 * DISP_DISP_WIN_OPTIONS register.
+	 */
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/display.h b/src/soc/nvidia/tegra132/include/soc/display.h
index 3378a4f2d2..b0f2573246 100644
--- a/src/soc/nvidia/tegra132/include/soc/display.h
+++ b/src/soc/nvidia/tegra132/include/soc/display.h
@@ -34,8 +34,12 @@
 	(mode->yres + mode->vfront_porch + \
 	mode->vsync_width + mode->vback_porch)
 
-struct soc_nvidia_tegra132_config;	/* forward declaration */
-
-int dsi_enable(struct soc_nvidia_tegra132_config *config);
-
+/* forward declaration */
+struct soc_nvidia_tegra132_config;
+struct display_controller;
+
+int tegra_dc_init(struct display_controller *disp_ctrl);
+int update_display_mode(struct display_controller *disp_ctrl,
+			struct soc_nvidia_tegra132_config *config);
+void update_window(const struct soc_nvidia_tegra132_config *config);
 #endif /* __SOC_NVIDIA_TEGRA132_INCLUDE_SOC_DISPLAY_H__ */