diff options
| author | Furquan Shaikh <furquan@google.com> | 2014-11-21 17:04:42 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 20:46:50 +0200 |
| commit | d56abd7d7a9b3b760dc6622858156474f689f1ef (patch) | |
| tree | 4c11e1c1e4f2728291d80e4f689cfec63ff4fc21 /src/soc/nvidia/tegra132/uart.c | |
| parent | b136d9f18c2a261b6772f08444afdddd7e9b1a53 (diff) | |
tegra132: Change memlayout to have PRERAM and POSTRAM CBFS Cache
Instead of having unified CBFS_CACHE and limiting the POSTRAM Cache size, split
them into PRERAM and POSTRAM CBFS_CACHE.
BUG=None
BRANCH=None
TEST=Compiles successfully for both rush and ryu. Boots to kernel prompt on ryu.
Change-Id: I2a70df22fe5bae23e05cdf1b8a300369c7ccf87d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b93bc06de76cab0a1ec9a56e12c9a6942a430893
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Change-Id: Iab21ff5c7ca880b6bd18846e5d8d71c26dff56cf
Original-Reviewed-on: https://chromium-review.googlesource.com/231546
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9535
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/uart.c')
0 files changed, 0 insertions, 0 deletions