diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-08-19 15:34:51 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-27 08:03:27 +0100 |
| commit | 913067d44f4daa2d58aacac0c33cb2938a0b3740 (patch) | |
| tree | 43c9f4d65aa39ba26e7af274cfba2820bac923c8 /src/soc/nvidia/tegra132/include | |
| parent | 9edf38ef1f366f10f1878cec34918934faf12dac (diff) | |
tegra132: initialize GIC
This provides are barebones initialization for tegra132 GIC
on CPU0. It routes all interrupts to CPU0, moves them all
into group 1, and attempts to allow non-secure access for
all registers (doesn't appear to be implemented, though).
BUG=chrome-os-partner:31449
BRANCH=None
TEST=Built and booted past smp init in the kernel. Timers
appear to be flowing now since jiffies are updated.
Change-Id: Id45c13cc23e50feed3d88da13420c9eb694498a0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 81bad0a53083baa7af0f1fd5f82fef0538ee62df
Original-Change-Id: I69dd9ae53f259e876a9bc4b9d7f65330150d2990
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/212795
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8995
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/nvidia/tegra132/include')
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/addressmap.h | 2 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra132/include/soc/ramstage.h | 26 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra132/include/soc/addressmap.h b/src/soc/nvidia/tegra132/include/soc/addressmap.h index 732c9e9366..ebe50f553e 100644 --- a/src/soc/nvidia/tegra132/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra132/include/soc/addressmap.h @@ -31,6 +31,8 @@ enum { enum { TEGRA_ARM_PERIPHBASE = 0x50040000, + TEGRA_GICD_BASE = 0x50041000, + TEGRA_GICC_BASE = 0x50042000, TEGRA_ARM_DISPLAYA = 0x54200000, TEGRA_ARM_DISPLAYB = 0x54240000, TEGRA_ARM_SOR = 0x54540000, diff --git a/src/soc/nvidia/tegra132/include/soc/ramstage.h b/src/soc/nvidia/tegra132/include/soc/ramstage.h new file mode 100644 index 0000000000..e42f56d687 --- /dev/null +++ b/src/soc/nvidia/tegra132/include/soc/ramstage.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA132_SOC_RAMSTAGE_H__ +#define __SOC_NVIDIA_TEGRA132_SOC_RAMSTAGE_H__ + +void gic_init(void); + +#endif /* __SOC_NVIDIA_TEGRA132_SOC_RAMSTAGE_H__ */ + |