diff options
| author | Andrew Bresticker <abrestic@chromium.org> | 2013-12-18 22:41:34 -0800 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-09-22 19:00:19 +0200 |
| commit | 24d4f7f8defca9c68d4a96ba5cbedf5b01ca6e53 (patch) | |
| tree | a38ef152b5381a72d68cef5e1860daffd1198227 /src/soc/nvidia/tegra124/display.c | |
| parent | d65e214d666269d0bd20d88ba2bc83349810c668 (diff) | |
tegra124/nyan: memory and display updates
tegra124: use pll_c_out1 as sclk parent
Reviewed-on: https://chromium-review.googlesource.com/180865
(cherry picked from commit 418337a5bde70df6a770222201c51bf3e8892d5f)
tegra124: take LP cluster out of reset
Reviewed-on: https://chromium-review.googlesource.com/180866
(cherry picked from commit 74cdc68ea9b29da9af313635787e82bacb9e23e3)
tegra124: norrin: display code clean up
Reviewed-on: https://chromium-review.googlesource.com/181003
(cherry picked from commit 63843ec61b3b47ffc985edcb589771591c5c9f17)
tegra124: Change the display hack to use window A
Reviewed-on: https://chromium-review.googlesource.com/182001
(cherry picked from commit ef245e42eb17b2eb0e8712f252353a95ee6fc01a)
tegra124: norrin: Initialize frame buffer
Reviewed-on: https://chromium-review.googlesource.com/182090
(cherry picked from commit b7c1d1b3c9519cbbe1615737aed4c4c0efed2167)
nyan: do not enable pull-ups on SPI1 (EC) data pins
Reviewed-on: https://chromium-review.googlesource.com/181063
(cherry picked from commit 2f55188501ebcae9e01b12831f152d4520c7047c)
tegra124: Add source for the LP0 resume blob.
Reviewed-on: https://chromium-review.googlesource.com/183152
(cherry picked from commit a00d099bf710c297320d7edff7f7c608283d1b0b)
tegra124: Revise Memory Controller registers structure definition.
Reviewed-on: https://chromium-review.googlesource.com/182992
(cherry picked from commit ae83564cdd1d46c8166df1a95703e8cb1060c0a1)
tegra124: Add more PMC register details.
Reviewed-on: https://chromium-review.googlesource.com/183231
(cherry picked from commit d62ed2c19693284f10c2a12f4295091de3ace829)
tegra124: Add SDRAM configuration header file from cbootimage.
Reviewed-on: https://chromium-review.googlesource.com/182613
(cherry picked from commit 193ed2a104af38f6c41a332a649ce06a3238e0a4)
tegra124: Revise sdram_param.h for Coreboot.
Reviewed-on: https://chromium-review.googlesource.com/182614
(cherry picked from commit 311b0568c5de627435a5b035a7a1e40ecc2672f8)
tegra124: Fix EMC base address.
Reviewed-on: https://chromium-review.googlesource.com/183602
(cherry picked from commit 587c8969292ccecfa29c7720bcf24c704ed4ac4e)
tegra124: Add EMC registers definition.
Reviewed-on: https://chromium-review.googlesource.com/183622
(cherry picked from commit 67a8e5c7e87a1cc6bf006ad806751b549ffd3d5a)
tegra124: Never touch MEM(MC)/EMC clocks in ramstage.
Reviewed-on: https://chromium-review.googlesource.com/183623
(cherry picked from commit 8e3bb34d4ae37feae89b4a39850b2988a334d023)
tegra124: use RAM_CODE[3:2] for ram code
Reviewed-on: https://chromium-review.googlesource.com/183833
(cherry picked from commit 0154239467064ffcbdb82fc4c6b629f5d0c3568d)
tegra124: Allow setting PLLM (clock for SDRAM).
Reviewed-on: https://chromium-review.googlesource.com/183621
(cherry picked from commit a534e5b7c61d655eedd409dbd7780a4f90d40683)
tegra124: SDRAM Initialization.
Reviewed-on: https://chromium-review.googlesource.com/182615
(cherry picked from commit 5a60ae93b0603ee0d4806132be0360f3b1612bce)
tegra124: Get RAM_CODE for SDRAM initialization.
Reviewed-on: https://chromium-review.googlesource.com/183781
(cherry picked from commit a5b7ce70525d7ffef3fac90b8eb14b3f3787f4d8)
Squashed 18 nyan/tegra commits for memory and display.
Change-Id: I59a781ee8dc2fd9c9085373f5a9bb7c8108b094c
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6914
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/nvidia/tegra124/display.c')
| -rw-r--r-- | src/soc/nvidia/tegra124/display.c | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 0572ce3181..ba357fd245 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -301,11 +301,6 @@ void display_startup(device_t dev) /* init dc_a */ init_dca_regs(); - /* init sor */ - init_sor_regs(); - - /* init dpaux */ - init_dpaux_regs(); /* power up perip */ dp_io_powerup(); @@ -313,13 +308,9 @@ void display_startup(device_t dev) /* bringup dp */ dp_bringup(framebuffer_base_mb*MiB); - { u16 *cp = (void *)(framebuffer_base_mb*MiB); - for(i = 0; i < 1048576*8; i++) - if (i % (1376 / 2) < 688 / 2) - cp[i] = 0x222; - else - cp[i] = 0x888; - } + /* init frame buffer */ + memset((void *)(framebuffer_base_mb*MiB), 0x00, + framebuffer_size_mb*MiB); /* tell depthcharge ... */ |