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authorRex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>2021-12-17 13:13:15 +0800
committerHung-Te Lin <hungte@chromium.org>2021-12-29 07:53:12 +0000
commitd67de90708331f1a68411f2c10bbe97fda919780 (patch)
tree20de4dedf287afe343ad43bd14a33ee35311df1f /src/soc/mediatek
parent783e2bff5357768be55e702791544459a8845fef (diff)
soc/mediatek/mt8186: Add DSI driver
Enable DSI for display. BUG=b:209930699 TEST=Firmware display looked good Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Idb6bd3a1d32ac96a9d1a2553b8a70db4e59eec16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek')
-rw-r--r--src/soc/mediatek/mt8186/Makefile.inc1
-rw-r--r--src/soc/mediatek/mt8186/include/soc/dsi.h60
2 files changed, 61 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc
index dd7541f222..f99bd47d47 100644
--- a/src/soc/mediatek/mt8186/Makefile.inc
+++ b/src/soc/mediatek/mt8186/Makefile.inc
@@ -46,6 +46,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
ramstage-y += ../common/auxadc.c
ramstage-y += ../common/ddp.c ddp.c
ramstage-y += devapc.c
+ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c
ramstage-y += emi.c
ramstage-y += ../common/flash_controller.c
ramstage-y += ../common/gpio.c gpio.c
diff --git a/src/soc/mediatek/mt8186/include/soc/dsi.h b/src/soc/mediatek/mt8186/include/soc/dsi.h
new file mode 100644
index 0000000000..2cb9159350
--- /dev/null
+++ b/src/soc/mediatek/mt8186/include/soc/dsi.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8186 Functional Specification
+ * Chapter number: 6.9
+ */
+
+#ifndef SOC_MEDIATEK_MT8186_DSI_H
+#define SOC_MEDIATEK_MT8186_DSI_H
+
+#include <soc/dsi_common.h>
+
+/* DSI features */
+#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
+#define MTK_DSI_MIPI_RATIO_DENOMINATOR 100
+#define MTK_DSI_DATA_RATE_MIN_MHZ 125
+#define MTK_DSI_HAVE_SIZE_CON 1
+#define PIXEL_STREAM_CUSTOM_HEADER 0xb
+
+/* MIPITX is SOC specific and cannot live in common. */
+
+/* MIPITX_REG */
+struct mipi_tx_regs {
+ u32 reserved0[3];
+ u32 lane_con;
+ u32 reserved1[6];
+ u32 pll_pwr;
+ u32 pll_con0;
+ u32 pll_con1;
+ u32 pll_con2;
+ u32 pll_con3;
+ u32 pll_con4;
+ u32 reserved2[65];
+ u32 d2_sw_ctl_en;
+ u32 reserved3[63];
+ u32 d0_sw_ctl_en;
+ u32 reserved4[56];
+ u32 ck_ckmode_en;
+ u32 reserved5[6];
+ u32 ck_sw_ctl_en;
+ u32 reserved6[63];
+ u32 d1_sw_ctl_en;
+ u32 reserved7[63];
+ u32 d3_sw_ctl_en;
+};
+
+check_member(mipi_tx_regs, pll_con4, 0x3c);
+check_member(mipi_tx_regs, d3_sw_ctl_en, 0x544);
+static struct mipi_tx_regs *const mipi_tx = (void *)MIPITX_BASE;
+
+/* Register values */
+#define DSI_CK_CKMODE_EN BIT(0)
+#define DSI_SW_CTL_EN BIT(0)
+#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
+#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
+
+#define RG_DSI_PLL_EN BIT(4)
+#define RG_DSI_PLL_POSDIV (0x7 << 8)
+
+#endif