diff options
| author | Sen Chu <sen.chu@mediatek.corp-partner.google.com> | 2023-08-16 08:44:41 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-23 12:12:54 +0000 |
| commit | 8cc8b3c14b07d03e4c702510b21d7e311049798e (patch) | |
| tree | ce7ddbf5978b7d0f3eba8bb3139ee71fe4016667 /src/soc/mediatek | |
| parent | 52354ea463caa168b2295dd742bcfe326c13f3f0 (diff) | |
soc/mediatek/mt8188: Simplify pmif init flow
Based on "MediaTek_EFUSE_MT8188_Confidential A_Technical Doc.docx",
MT8188G used in ChromeOS project does not support clock hardware
monitor. Thus, we can simplify the initialization flow by removing the
hardware default value check.
BUG=b:292866009
TEST=emerge-geralt coreboot
BRANCH=none
Change-Id: I07cd753f153da5b0aea1518a04a818214f986aeb
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77334
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek')
| -rw-r--r-- | src/soc/mediatek/mt8188/pmif_clk.c | 19 |
1 files changed, 5 insertions, 14 deletions
diff --git a/src/soc/mediatek/mt8188/pmif_clk.c b/src/soc/mediatek/mt8188/pmif_clk.c index 0a943254f1..9756f99d1a 100644 --- a/src/soc/mediatek/mt8188/pmif_clk.c +++ b/src/soc/mediatek/mt8188/pmif_clk.c @@ -121,20 +121,11 @@ static int pmif_init_ulposc(void) int pmif_clk_init(void) { - u32 ulposc1; - - /* check hardware default value first */ - ulposc1 = pmif_get_ulposc_freq_mhz(CALI_DEFAULT_CAP_VALUE); - if (pmif_ulposc_check(ulposc1, FREQ_260MHZ)) { - /* - * If the hardware value is not what we want, we need to adjust - * it by the software setting. - */ - pmif_clockmonitor_config(false); - if (pmif_init_ulposc()) - return E_NODEV; - pmif_clockmonitor_config(true); - } + /* initialize pmif clock */ + pmif_clockmonitor_config(false); + if (pmif_init_ulposc()) + return E_NODEV; + pmif_clockmonitor_config(true); /* turn off pmic_cg_tmr, cg_ap, cg_md, cg_conn clock */ SET32_BITFIELDS(&mt8188_infracfg_ao->module_sw_cg_0_set, PMIC_CG_TMR, 1, PMIC_CG_AP, 1, |