soc/mediatek/mt8196: Fix timer reset in BL31

After reboot, the system does not need to serve pending IRQ from
systimer. Therefore, clear systimer IRQ pending bits in init_timer().
For that to work, the systimer compensation version 2.0 needs to be
enabled.

TEST=Build pass and timestamp is not reset in ATF and payload
BUG=b:343881008

Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59
Signed-off-by: Zhanzhan Ge <zhanzhan.ge@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83928
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

1 files changed, 34 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8196/timer_prepare.c b/src/soc/mediatek/mt8196/timer_prepare.c
new file mode 100644
index 0000000000..08496e83d8
--- /dev/null
+++ b/src/soc/mediatek/mt8196/timer_prepare.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on MT8196 Functional Specification
+ * Chapter number: 1.2 2.2
+ */
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+#include <soc/timer.h>
+
+static void clear_systimer(struct systimer *const mtk_systimer)
+{
+	unsigned int id = 0;
+
+	for (id = 0; id < SYSTIMER_CNT; id++) {
+		u32 *cnttval_con = &mtk_systimer->cnttval[id].con;
+		WRITE32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_EN);
+		SET32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_IRQ_CLR);
+		WRITE32_BITFIELDS(cnttval_con, SYST_CON, SYST_CON_CLR);
+	}
+
+	SET32_BITFIELDS(&mtk_systimer->cntcr, REV_SET, REV_CLR_EN);
+}
+
+void timer_prepare(void)
+{
+	struct systimer *mtk_systimer = (void *)SYSTIMER_BASE;
+
+	SET32_BITFIELDS(&mtk_systimer->cntcr,
+			COMP_FEATURE, COMP_FEATURE_CLR | COMP_FEATURE_20_EN,
+			COMP_FEATURE_TIE, COMP_FEATURE_TIE_CLR | COMP_FEATURE_TIE_EN);
+	clear_systimer(mtk_systimer);
+}