diff options
| author | Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> | 2024-07-14 19:02:21 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-09-30 11:11:01 +0000 |
| commit | ced0c208e43ebcdf9560754a6db27d10ae7df81f (patch) | |
| tree | 70afc6bb88e628be7c0e1c16f4be11fdaf7ba55c /src/soc/mediatek/mt8196/timer.c | |
| parent | 16fe2eec083fa9465b157a322111cd6678a306d4 (diff) | |
soc/mediatek/mt8196: Fix timer reset in BL31
After reboot, the system does not need to serve pending IRQ from
systimer. Therefore, clear systimer IRQ pending bits in init_timer().
For that to work, the systimer compensation version 2.0 needs to be
enabled.
TEST=Build pass and timestamp is not reset in ATF and payload
BUG=b:343881008
Change-Id: I520986b81ca153ec3ce56558a80619448cfc0c59
Signed-off-by: Zhanzhan Ge <zhanzhan.ge@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83928
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8196/timer.c')
| -rw-r--r-- | src/soc/mediatek/mt8196/timer.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8196/timer.c b/src/soc/mediatek/mt8196/timer.c index 9d8dd7a9a6..bf3f3cee63 100644 --- a/src/soc/mediatek/mt8196/timer.c +++ b/src/soc/mediatek/mt8196/timer.c @@ -3,8 +3,11 @@ #include <arch/lib_helpers.h> #include <commonlib/helpers.h> #include <delay.h> +#include <soc/timer.h> void init_timer(void) { - raw_write_cntfrq_el0(13 * MHz); + timer_prepare(); + + raw_write_cntfrq_el0(GPT_MHZ * MHz); } |