diff options
| author | Yidi Lin <yidilin@chromium.org> | 2024-10-15 16:43:39 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2024-10-23 06:35:46 +0000 |
| commit | af3f8298d62832d1bb2bee4ef08097052e07c1a7 (patch) | |
| tree | 44e17618b22cc55ca6185010770c1e01fef66107 /src/soc/mediatek/mt8195 | |
| parent | 16062b582a7e4ea405eb58a9df8cfe5279b2684b (diff) | |
soc/mediatek/common: Config CAL_TOL_RATE and CAL_MAX_VAL in SoC folder
MT8196 has differenet configurations from other platforms. Make
CAL_TOL_RATE and CAL_MAX_VAL as per SoC configuration in order to reuse
common/pmif_clk.c
BUG=none
TEST=emerge-corsola coreboot; emerge-geralt coreboot
Change-Id: Iefc8180e1719d9796df7457b619a8792ceb762b2
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84771
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8195')
| -rw-r--r-- | src/soc/mediatek/mt8195/include/soc/pmif.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/include/soc/pmif.h b/src/soc/mediatek/mt8195/include/soc/pmif.h index ab293b2d66..7ee9531917 100644 --- a/src/soc/mediatek/mt8195/include/soc/pmif.h +++ b/src/soc/mediatek/mt8195/include/soc/pmif.h @@ -140,5 +140,11 @@ enum { FREQ_248MHZ = 248, }; +/* calibation tolerance rate, unit: 0.1% */ +enum { + CAL_TOL_RATE = 40, + CAL_MAX_VAL = 0x7F, +}; + #define FREQ_METER_ABIST_AD_OSC_CK 48 #endif /*__MT8195_SOC_PMIF_H__*/ |