soc/mediatek/mt8195: add register definitions

Add register definitions for infracfg_ao, topckgen, apmixed and SPM.

Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Ie740f22aa12f40950a27a3e0142e2d50a506b251
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

3 files changed, 1445 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8195/include/soc/infracfg.h b/src/soc/mediatek/mt8195/include/soc/infracfg.h
new file mode 100644
index 0000000000..adb5ff00ed
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/infracfg.h
@@ -0,0 +1,412 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_INFRACFG_H
+#define SOC_MEDIATEK_MT8195_INFRACFG_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8195_infracfg_ao_regs {
+	u32 reserved1[20];
+	u32 infra_globalcon_dcmctl;	/* 0x0050 */
+	u32 reserved2[7];
+	u32 infra_bus_dcm_ctrl;	/* 0x0070 */
+	u32 peri_bus_dcm_ctrl;
+	u32 mem_dcm_ctrl;
+	u32 dfs_mem_dcm_ctrl;
+	u32 module_sw_cg_0_set;
+	u32 module_sw_cg_0_clr;
+	u32 module_sw_cg_1_set;
+	u32 module_sw_cg_1_clr;
+	u32 module_sw_cg_0_sta;
+	u32 module_sw_cg_1_sta;
+	u32 module_clk_sel;
+	u32 mem_cg_ctrl;
+	u32 p2p_rx_clk_on;
+	u32 module_sw_cg_2_set;
+	u32 module_sw_cg_2_clr;
+	u32 module_sw_cg_2_sta;
+	u32 reserved3[1];
+	u32 dramc_wbr;	/* 0x00b4 */
+	u32 reserved4[2];
+	u32 module_sw_cg_3_set;	/* 0x00c0 */
+	u32 module_sw_cg_3_clr;
+	u32 module_sw_cg_3_sta;
+	u32 reserved5[5];
+	u32 module_sw_cg_4_set;	/* 0x00e0 */
+	u32 module_sw_cg_4_clr;
+	u32 module_sw_cg_4_sta;
+	u32 reserved6[5];
+	u32 i2c_dbtool_misc;	/* 0x0100 */
+	u32 md_sleep_ctrl_mask;
+	u32 pmicw_clock_ctrl;
+	u32 reserved7[5];
+	u32 infra_globalcon_rst0_set;	/* 0x0120 */
+	u32 infra_globalcon_rst0_clr;
+	u32 infra_globalcon_rst0_sta;
+	u32 reserved8[1];
+	u32 infra_globalcon_rst1_set;	/* 0x0130 */
+	u32 infra_globalcon_rst1_clr;
+	u32 infra_globalcon_rst1_sta;
+	u32 reserved9[1];
+	u32 infra_globalcon_rst2_set;	/* 0x0140 */
+	u32 infra_globalcon_rst2_clr;
+	u32 infra_globalcon_rst2_sta;
+	u32 reserved10[1];
+	u32 infra_globalcon_rst3_set;	/* 0x0150 */
+	u32 infra_globalcon_rst3_clr;
+	u32 infra_globalcon_rst3_sta;
+	u32 reserved11[37];
+	u32 infra_nna0_slave_gals_ctrl;	/* 0x01f0 */
+	u32 infra_nna1_slave_gals_ctrl;
+	u32 infra_nna0_master_gals_ctrl;
+	u32 infra_nna1_master_gals_ctrl;
+	u32 infra_topaxi_si0_ctl;
+	u32 infra_topaxi_si1_ctl;
+	u32 infra_topaxi_mdbus_ctl;
+	u32 infra_mci_si0_ctl;
+	u32 infra_mci_si1_ctl;
+	u32 infra_mci_si2_ctl;
+	u32 infra_mci_async_ctl;
+	u32 infra_mci_cg_mfg_sec_sta;
+	u32 infra_topaxi_protecten;
+	u32 infra_topaxi_protecten_sta0;
+	u32 infra_topaxi_protecten_sta1;
+	u32 reserved12[1];
+	u32 infra_apb_async_sta;	/* 0x0230 */
+	u32 infra_topaxi_si2_ctl;
+	u32 infra_topaxi_fmem_mdhw_ctrl;
+	u32 infra_conn_gals_ctl;
+	u32 infra_mci_trans_con_read;
+	u32 infra_mci_trans_con_write;
+	u32 infra_mci_id_remap_con;
+	u32 infra_mci_emi_trans_con;
+	u32 infra_topaxi_protecten_1;
+	u32 infra_topaxi_protecten_sta0_1;
+	u32 infra_topaxi_protecten_sta1_1;
+	u32 reserved13[1];
+	u32 infra_topaxi_aslice_ctrl;	/* 0x0260 */
+	u32 infra_topaxi_aslice_ctrl_1;
+	u32 infra_topaxi_aslice_ctrl_2;
+	u32 infra_topaxi_aslice_ctrl_3;
+	u32 infra_topaxi_mi_ctrl;
+	u32 infra_topaxi_cbip_aslice_ctrl;
+	u32 infra_topaxi_cbip_slice_ctrl;
+	u32 infra_top_master_sideband;
+	u32 infra_ssusb_dev;
+	u32 reserved14[1];
+	u32 infra_topaxi_emi_gmc_l2c_ctrl;	/* 0x0288 */
+	u32 infra_topaxi_cbip_slice_ctrl_1;
+	u32 infra_mfg_slave_gals_ctrl;
+	u32 infra_mfg_master_m0_gals_ctrl;
+	u32 infra_mfg_master_m1_gals_ctrl;
+	u32 infra_top_master_sideband_1;
+	u32 infra_topaxi_protecten_set;
+	u32 infra_topaxi_protecten_clr;
+	u32 infra_topaxi_protecten_1_set;
+	u32 infra_topaxi_protecten_1_clr;
+	u32 infra_topaxi_cbip_slice_ctrl_2;
+	u32 reserved15[1];
+	u32 infra_topaxi_aslice_ctrl_4;	/* 0x02b8 */
+	u32 reserved16[1];
+	u32 infra_topaxi_protecten_mcu;	/* 0x02c0 */
+	u32 infra_topaxi_protecten_mcu_set;
+	u32 infra_topaxi_protecten_mcu_clr;
+	u32 reserved17[1];
+	u32 infra_topaxi_protecten_mm;	/* 0x02d0 */
+	u32 infra_topaxi_protecten_mm_set;
+	u32 infra_topaxi_protecten_mm_clr;
+	u32 reserved18[1];
+	u32 infra_topaxi_protecten_mcu_sta0;	/* 0x02e0 */
+	u32 infra_topaxi_protecten_mcu_sta1;
+	u32 infra_topaxi_protecten_mm_sta0;
+	u32 infra_topaxi_protecten_mm_sta1;
+	u32 reserved19[1];
+	u32 infra_apu_master_m0_gals_ctl;	/* 0x02f4 */
+	u32 infra_apu_master_m1_gals_ctl;
+	u32 infra_topaxi_bus_dbg_con_ao;
+	u32 md1_bank0_map0;
+	u32 md1_bank0_map1;
+	u32 md1_bank0_map2;
+	u32 md1_bank0_map3;
+	u32 md1_bank1_map0;
+	u32 md1_bank1_map1;
+	u32 md1_bank1_map2;
+	u32 md1_bank1_map3;
+	u32 md1_bank4_map0;
+	u32 md1_bank4_map1;
+	u32 md1_bank4_map2;
+	u32 md1_bank4_map3;
+	u32 md2_bank0_map0;
+	u32 md2_bank0_map1;
+	u32 md2_bank0_map2;
+	u32 md2_bank0_map3;
+	u32 reserved20[4];
+	u32 md2_bank4_map0;	/* 0x0350 */
+	u32 md2_bank4_map1;
+	u32 md2_bank4_map2;
+	u32 md2_bank4_map3;
+	u32 c2k_config;
+	u32 c2k_status;
+	u32 c2k_spm_ctrl;
+	u32 reserved21[1];
+	u32 ap2md_dummy;	/* 0x0370 */
+	u32 reserved22[3];
+	u32 conn_map0;	/* 0x0380 */
+	u32 cldma_map0;
+	u32 conn_map1;
+	u32 conn_bus_con;
+	u32 mcusys_dfd_map;
+	u32 conn_map2;
+	u32 conn_map3;
+	u32 conn_map4;
+	u32 module_clk_sel_set;
+	u32 module_clk_sel_clr;
+	u32 pmicw_clock_ctrl_set;
+	u32 pmicw_clock_ctrl_clr;
+	u32 dramc_wbr_set;
+	u32 dramc_wbr_clr;
+	u32 topaxi_si0_ctl_set;
+	u32 topaxi_si0_ctl_clr;
+	u32 topaxi_si1_ctl_set;
+	u32 topaxi_si1_ctl_clr;
+	u32 reserved23[14];
+	u32 peri_cci_sideband_con;	/* 0x0400 */
+	u32 mfg_cci_sideband_con;
+	u32 reserved24[2];
+	u32 infra_pwm_cksw_ctrl;	/* 0x0410 */
+	u32 reserved25[59];
+	u32 infra_ao_dbg_con0;	/* 0x0500 */
+	u32 infra_ao_dbg_con1;
+	u32 infra_ao_dbg_con2;
+	u32 infra_ao_dbg_con3;
+	u32 md_dbg_ck_con;
+	u32 infra_ao_dbg_sta;
+	u32 reserved26[58];
+	u32 mfg_misc_con;	/* 0x0600 */
+	u32 reserved27[3];
+	u32 infracfg_ao_iommu_0;	/* 0x0610 */
+	u32 infracfg_ao_iommu_1;
+	u32 reserved28[58];
+	u32 infra_rsvd0;	/* 0x0700 */
+	u32 infra_rsvd1;
+	u32 infra_rsvd2;
+	u32 infra_rsvd3;
+	u32 infra_topaxi_protecten_2;
+	u32 infra_topaxi_protecten_set_2;
+	u32 infra_topaxi_protecten_clr_2;
+	u32 reserved29[1];
+	u32 infra_topaxi_protecten_sta0_2;	/* 0x0720 */
+	u32 infra_topaxi_protecten_sta1_2;
+	u32 reserved30[2];
+	u32 infra_globalcon_rst4_set;	/* 0x0730 */
+	u32 infra_globalcon_rst4_clr;
+	u32 infra_globalcon_rst4_sta;
+	u32 infra_ao_sec_rst_con4;
+	u32 reserved31[16];
+	u32 mcu2emi_m0_parity;	/* 0x0780 */
+	u32 mcu2emi_m0_parity_dbg_aw_1;
+	u32 mcu2emi_m0_parity_dbg_aw_2;
+	u32 mcu2emi_m0_parity_dbg_ar_1;
+	u32 mcu2emi_m0_parity_dbg_ar_2;
+	u32 mcu2emi_m1_parity;
+	u32 mcu2emi_m1_parity_dbg_aw_1;
+	u32 mcu2emi_m1_parity_dbg_aw_2;
+	u32 mcu2emi_m1_parity_dbg_ar_1;
+	u32 mcu2emi_m1_parity_dbg_ar_2;
+	u32 mcu2ifr_reg_parity;
+	u32 mcu2ifr_reg_parity_dbg_aw_1;
+	u32 mcu2ifr_reg_parity_dbg_aw_2;
+	u32 mcu2ifr_reg_parity_dbg_ar_1;
+	u32 mcu2ifr_reg_parity_dbg_ar_2;
+	u32 ifr_l3c2mcu_parity;
+	u32 ifr_l3c2mcu_parity_dbg_r_1;
+	u32 reserved32[27];
+	u32 gcpu_aor_ctrl;	/* 0x0830 */
+	u32 gcpu_aor_lock_sbc_pubk_hv;
+	u32 reserved33[2];
+	u32 gcpu_aor_sbc_pubk_hv0;	/* 0x0840 */
+	u32 gcpu_aor_sbc_pubk_hv1;
+	u32 gcpu_aor_sbc_pubk_hv2;
+	u32 gcpu_aor_sbc_pubk_hv3;
+	u32 gcpu_aor_sbc_pubk_hv4;
+	u32 gcpu_aor_sbc_pubk_hv5;
+	u32 gcpu_aor_sbc_pubk_hv6;
+	u32 gcpu_aor_sbc_pubk_hv7;
+	u32 gcpu_aor_sbc_pubk_hv8;
+	u32 gcpu_aor_sbc_pubk_hv9;
+	u32 gcpu_aor_sbc_pubk_hv10;
+	u32 gcpu_aor_sbc_pubk_hv11;
+	u32 reserved34[36];
+	u32 infra_bonding;	/* 0x0900 */
+	u32 reserved35[63];
+	u32 infra_ao_scpsys_apb_async_sta;	/* 0x0a00 */
+	u32 infra_ao_md32_tx_apb_async_sta;
+	u32 infra_ao_md32_rx_apb_async_sta;
+	u32 infra_ao_cksys_apb_async_sta;
+	u32 infra_ao_pmic_wrap_tx_apb_async_sta;
+	u32 infra_mcu2apu_asl0_ctl;
+	u32 infra_mcu2reg_asl0_ctl;
+	u32 infra_mcu_decoder_infra_ctl;
+	u32 infra_mcu_decoder_sta0;
+	u32 infra_mcu_decoder_sta1;
+	u32 infra_idle_async_bit_en_0;
+	u32 infra_apu_slave_gals_ctrl;
+	u32 infra_aximem_idle_bit_en_0;
+	u32 infra_mcu_path_sync_ctl;
+	u32 infra_conn2ap_int_mask;
+	u32 infra_mcu_pwr_ctl_mask;
+	u32 infra_md_rsv;
+	u32 reserved36[7];
+	u32 infra_mem_26m_cksel;	/* 0x0a60 */
+	u32 reserved37[39];
+	u32 pll_ulposc_con0;	/* 0x0b00 */
+	u32 pll_ulposc_con1;
+	u32 reserved38[2];
+	u32 pll_auxadc_con0;	/* 0x0b10 */
+	u32 scp_infra_irq_set;
+	u32 scp_infra_irq_clr;
+	u32 scp_infra_ctrl;
+	u32 reserved39[24];
+	u32 infra_topaxi_protecten_vdnr;	/* 0x0b80 */
+	u32 infra_topaxi_protecten_vdnr_set;
+	u32 infra_topaxi_protecten_vdnr_clr;
+	u32 infra_topaxi_protecten_vdnr_sta0;
+	u32 infra_topaxi_protecten_vdnr_sta1;
+	u32 reserved40[3];
+	u32 infra_topaxi_protecten_vdnr_1;	/* 0x0ba0 */
+	u32 infra_topaxi_protecten_vdnr_set_1;
+	u32 infra_topaxi_protecten_vdnr_clr_1;
+	u32 infra_topaxi_protecten_vdnr_sta0_1;
+	u32 infra_topaxi_protecten_vdnr_sta1_1;
+	u32 infra_topaxi_protecten_vdnr_2;
+	u32 infra_topaxi_protecten_vdnr_set_2;
+	u32 infra_topaxi_protecten_vdnr_clr_2;
+	u32 infra_topaxi_protecten_vdnr_sta0_2;
+	u32 infra_topaxi_protecten_vdnr_sta1_2;
+	u32 infra_topaxi_protecten_sub_infra_vdnr;
+	u32 infra_topaxi_protecten_sub_infra_vdnr_set;
+	u32 infra_topaxi_protecten_sub_infra_vdnr_clr;
+	u32 infra_topaxi_protecten_sub_infra_vdnr_sta0;
+	u32 infra_topaxi_protecten_sub_infra_vdnr_sta1;
+	u32 reserved41[9];
+	u32 cldma_ctrl;	/* 0x0c00 */
+	u32 reserved42[63];
+	u32 infrabus_dbg0;	/* 0x0d00 */
+	u32 infrabus_dbg1;
+	u32 infrabus_dbg2;
+	u32 infrabus_dbg3;
+	u32 infrabus_dbg4;
+	u32 infrabus_dbg5;
+	u32 infrabus_dbg6;
+	u32 infrabus_dbg7;
+	u32 infrabus_dbg8;
+	u32 infrabus_dbg9;
+	u32 infrabus_dbg10;
+	u32 infrabus_dbg11;
+	u32 infrabus_dbg12;
+	u32 infrabus_dbg13;
+	u32 infrabus_dbg14;
+	u32 infrabus_dbg15;
+	u32 infrabus_dbg16;
+	u32 infrabus_dbg17;
+	u32 infrabus_dbg18;
+	u32 infrabus_dbg19;
+	u32 infrabus_dbg20;
+	u32 infrabus_dbg21;
+	u32 infrabus_dbg22;
+	u32 infrabus_dbg23;
+	u32 infrabus_dbg24;
+	u32 infrabus_dbg25;
+	u32 infrabus_dbg26;
+	u32 infrabus_dbg27;
+	u32 infrabus_dbg28;
+	u32 infrabus_dbg29;
+	u32 infrabus_dbg30;
+	u32 infrabus_dbg31;
+	u32 infrabus_dbg32;
+	u32 infrabus_dbg33;
+	u32 infrabus_dbg34;
+	u32 infrabus_dbg35;
+	u32 infrabus_dbg36;
+	u32 infrabus_dbg37;
+	u32 infrabus_dbg38;
+	u32 infrabus_dbg39;
+	u32 infrabus_dbg40;
+	u32 infrabus_dbg41;
+	u32 infrabus_dbg42;
+	u32 infrabus_dbg43;
+	u32 infrabus_dbg44;
+	u32 infrabus_dbg45;
+	u32 reserved43[4];
+	u32 infra_topaxi_protecten_mm_2;	/* 0x0dc8 */
+	u32 infra_topaxi_protecten_mm_set_2;
+	u32 infra_topaxi_protecten_mm_clr_2;
+	u32 infra_topaxi_protecten_mm_sta0_2;
+	u32 infra_topaxi_protecten_mm_sta1_2;
+	u32 reserved44[5];
+	u32 infrabus_dbg_mask2;	/* 0x0df0 */
+	u32 reserved45[67];
+	u32 infra_misc;	/* 0x0f00 */
+	u32 infra_acp;
+	u32 misc_config;
+	u32 infra_misc2;
+	u32 mdsys_misc_con;
+	u32 reserved46[27];
+	u32 infra_ao_sec_con;	/* 0x0f80 */
+	u32 infra_ao_sec_cg_con0;
+	u32 infra_ao_sec_cg_con1;
+	u32 infra_ao_sec_rst_con0;
+	u32 infra_ao_sec_rst_con1;
+	u32 infra_ao_sec_rst_con2;
+	u32 reserved47[1];
+	u32 infra_ao_sec_cg_con2;	/* 0x0f9c */
+	u32 infra_ao_sec_rst_con3;
+	u32 infra_ao_sec_cg_con3;
+	u32 reserved48[2];
+	u32 infra_ao_sec_hyp;	/* 0x0fb0 */
+	u32 infra_ao_sec_mfg_hyp;
+};
+
+check_member(mt8195_infracfg_ao_regs, infra_globalcon_dcmctl, 0x0050);
+check_member(mt8195_infracfg_ao_regs, infra_bus_dcm_ctrl, 0x0070);
+check_member(mt8195_infracfg_ao_regs, module_sw_cg_0_clr, 0x0084);
+check_member(mt8195_infracfg_ao_regs, module_sw_cg_1_clr, 0x008c);
+check_member(mt8195_infracfg_ao_regs, module_sw_cg_2_clr, 0x00a8);
+check_member(mt8195_infracfg_ao_regs, module_sw_cg_3_set, 0x00c0);
+check_member(mt8195_infracfg_ao_regs, module_sw_cg_4_set, 0x00e0);
+check_member(mt8195_infracfg_ao_regs, i2c_dbtool_misc, 0x0100);
+check_member(mt8195_infracfg_ao_regs, infra_globalcon_rst0_set, 0x0120);
+check_member(mt8195_infracfg_ao_regs, infra_nna0_slave_gals_ctrl, 0x01f0);
+check_member(mt8195_infracfg_ao_regs, md2_bank4_map0, 0x0350);
+check_member(mt8195_infracfg_ao_regs, conn_map0, 0x0380);
+check_member(mt8195_infracfg_ao_regs, peri_cci_sideband_con, 0x0400);
+check_member(mt8195_infracfg_ao_regs, infra_pwm_cksw_ctrl, 0x0410);
+check_member(mt8195_infracfg_ao_regs, infra_ao_dbg_con0, 0x0500);
+check_member(mt8195_infracfg_ao_regs, mfg_misc_con, 0x0600);
+check_member(mt8195_infracfg_ao_regs, infracfg_ao_iommu_0, 0x0610);
+check_member(mt8195_infracfg_ao_regs, infra_rsvd0, 0x0700);
+check_member(mt8195_infracfg_ao_regs, infra_globalcon_rst4_set, 0x0730);
+check_member(mt8195_infracfg_ao_regs, mcu2emi_m0_parity, 0x0780);
+check_member(mt8195_infracfg_ao_regs, gcpu_aor_ctrl, 0x0830);
+check_member(mt8195_infracfg_ao_regs, gcpu_aor_sbc_pubk_hv0, 0x0840);
+check_member(mt8195_infracfg_ao_regs, infra_bonding, 0x0900);
+check_member(mt8195_infracfg_ao_regs, infra_ao_scpsys_apb_async_sta, 0x0a00);
+check_member(mt8195_infracfg_ao_regs, infra_mem_26m_cksel, 0x0a60);
+check_member(mt8195_infracfg_ao_regs, pll_ulposc_con0, 0x0b00);
+check_member(mt8195_infracfg_ao_regs, pll_auxadc_con0, 0x0b10);
+check_member(mt8195_infracfg_ao_regs, infra_topaxi_protecten_vdnr, 0x0b80);
+check_member(mt8195_infracfg_ao_regs, infra_topaxi_protecten_vdnr_1, 0x0ba0);
+check_member(mt8195_infracfg_ao_regs, cldma_ctrl, 0x0c00);
+check_member(mt8195_infracfg_ao_regs, infrabus_dbg0, 0x0d00);
+check_member(mt8195_infracfg_ao_regs, infra_topaxi_protecten_mm_2, 0x0dc8);
+check_member(mt8195_infracfg_ao_regs, infrabus_dbg_mask2, 0x0df0);
+check_member(mt8195_infracfg_ao_regs, infra_misc, 0x0f00);
+check_member(mt8195_infracfg_ao_regs, infra_ao_sec_con, 0x0f80);
+check_member(mt8195_infracfg_ao_regs, infra_ao_sec_hyp, 0x0fb0);
+check_member(mt8195_infracfg_ao_regs, infra_ao_sec_mfg_hyp, 0x0fb4);
+
+static struct mt8195_infracfg_ao_regs *const mt8195_infracfg_ao =
+	(void *)INFRACFG_AO_BASE;
+
+#endif	/* SOC_MEDIATEK_MT8195_INFRACFG_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/pll.h b/src/soc/mediatek/mt8195/include/soc/pll.h
index b8a36fd1ec..e2240ed195 100644
--- a/src/soc/mediatek/mt8195/include/soc/pll.h
+++ b/src/soc/mediatek/mt8195/include/soc/pll.h
@@ -3,8 +3,505 @@
 #ifndef SOC_MEDIATEK_MT8195_PLL_H
 #define SOC_MEDIATEK_MT8195_PLL_H
 
+#include <device/mmio.h>
+#include <types.h>
 #include <soc/pll_common.h>
 
+struct mtk_topckgen_regs {
+	u32 reserved1[1];
+	u32 clk_cfg_update;	/* 0x0004 */
+	u32 clk_cfg_update1;
+	u32 clk_cfg_update2;
+	u32 clk_cfg_update3;
+	u32 clk_cfg_update4;
+	u32 reserved2[2];
+	u32 clk_cfg_0;	/* 0x0020 */
+	u32 clk_cfg_0_set;
+	u32 clk_cfg_0_clr;
+	u32 clk_cfg_1;
+	u32 clk_cfg_1_set;
+	u32 clk_cfg_1_clr;
+	u32 clk_cfg_2;
+	u32 clk_cfg_2_set;
+	u32 clk_cfg_2_clr;
+	u32 clk_cfg_3;
+	u32 clk_cfg_3_set;
+	u32 clk_cfg_3_clr;
+	u32 clk_cfg_4;
+	u32 clk_cfg_4_set;
+	u32 clk_cfg_4_clr;
+	u32 clk_cfg_5;
+	u32 clk_cfg_5_set;
+	u32 clk_cfg_5_clr;
+	u32 clk_cfg_6;
+	u32 clk_cfg_6_set;
+	u32 clk_cfg_6_clr;
+	u32 clk_cfg_7;
+	u32 clk_cfg_7_set;
+	u32 clk_cfg_7_clr;
+	u32 clk_cfg_8;
+	u32 clk_cfg_8_set;
+	u32 clk_cfg_8_clr;
+	u32 clk_cfg_9;
+	u32 clk_cfg_9_set;
+	u32 clk_cfg_9_clr;
+	u32 clk_cfg_10;
+	u32 clk_cfg_10_set;
+	u32 clk_cfg_10_clr;
+	u32 clk_cfg_11;
+	u32 clk_cfg_11_set;
+	u32 clk_cfg_11_clr;
+	u32 clk_cfg_12;
+	u32 clk_cfg_12_set;
+	u32 clk_cfg_12_clr;
+	u32 clk_cfg_13;
+	u32 clk_cfg_13_set;
+	u32 clk_cfg_13_clr;
+	u32 clk_cfg_14;
+	u32 clk_cfg_14_set;
+	u32 clk_cfg_14_clr;
+	u32 clk_cfg_15;
+	u32 clk_cfg_15_set;
+	u32 clk_cfg_15_clr;
+	u32 clk_cfg_16;
+	u32 clk_cfg_16_set;
+	u32 clk_cfg_16_clr;
+	u32 clk_cfg_17;
+	u32 clk_cfg_17_set;
+	u32 clk_cfg_17_clr;
+	u32 clk_cfg_18;
+	u32 clk_cfg_18_set;
+	u32 clk_cfg_18_clr;
+	u32 clk_cfg_19;
+	u32 clk_cfg_19_set;
+	u32 clk_cfg_19_clr;
+	u32 clk_cfg_20;
+	u32 clk_cfg_20_set;
+	u32 clk_cfg_20_clr;
+	u32 clk_cfg_21;
+	u32 clk_cfg_21_set;
+	u32 clk_cfg_21_clr;
+	u32 clk_cfg_22;
+	u32 clk_cfg_22_set;
+	u32 clk_cfg_22_clr;
+	u32 clk_cfg_23;
+	u32 clk_cfg_23_set;
+	u32 clk_cfg_23_clr;
+	u32 clk_cfg_24;
+	u32 clk_cfg_24_set;
+	u32 clk_cfg_24_clr;
+	u32 clk_cfg_25;
+	u32 clk_cfg_25_set;
+	u32 clk_cfg_25_clr;
+	u32 clk_cfg_26;
+	u32 clk_cfg_26_set;
+	u32 clk_cfg_26_clr;
+	u32 clk_cfg_27;
+	u32 clk_cfg_27_set;
+	u32 clk_cfg_27_clr;
+	u32 clk_cfg_28;
+	u32 clk_cfg_28_set;
+	u32 clk_cfg_28_clr;
+	u32 clk_cfg_29;
+	u32 clk_cfg_29_set;
+	u32 clk_cfg_29_clr;
+	u32 clk_cfg_30;
+	u32 clk_cfg_30_set;
+	u32 clk_cfg_30_clr;
+	u32 clk_cfg_31;
+	u32 clk_cfg_31_set;
+	u32 clk_cfg_31_clr;
+	u32 clk_cfg_32;
+	u32 clk_cfg_32_set;
+	u32 clk_cfg_32_clr;
+	u32 clk_cfg_33;
+	u32 clk_cfg_33_set;
+	u32 clk_cfg_33_clr;
+	u32 clk_cfg_34;
+	u32 clk_cfg_34_set;
+	u32 clk_cfg_34_clr;
+	u32 clk_cfg_35;
+	u32 clk_cfg_35_set;
+	u32 clk_cfg_35_clr;
+	u32 clk_cfg_36;
+	u32 clk_cfg_36_set;
+	u32 clk_cfg_36_clr;
+	u32 clk_cfg_37;
+	u32 clk_cfg_37_set;
+	u32 clk_cfg_37_clr;
+	u32 reserved3[7];
+	u32 clk_extck_reg;	/* 0x0204 */
+	u32 reserved4[1];
+	u32 clk_dbg_cfg;	/* 0x020c */
+	u32 reserved5[2];
+	u32 clk26cali_0;	/* 0x0218 */
+	u32 clk26cali_1;
+	u32 reserved6[3];
+	u32 clk_misc_cfg_0;	/* 0x022c */
+	u32 reserved7[2];
+	u32 clk_misc_cfg_1;	/* 0x0238 */
+	u32 reserved8[2];
+	u32 clk_misc_cfg_2;	/* 0x0244 */
+	u32 reserved9[2];
+	u32 clk_misc_cfg_3;	/* 0x0250 */
+	u32 reserved10[2];
+	u32 clk_misc_cfg_6;	/* 0x025c */
+	u32 reserved11[1];
+	u32 clk_scp_cfg_0;	/* 0x0264 */
+	u32 reserved12[13];
+	u32 clkmon_clk_sel;	/* 0x029c */
+	u32 clkmon_k1;
+	u32 reserved13[6];
+	u32 cksta_reg_0;	/* 0x02bc */
+	u32 cksta_reg_1;
+	u32 cksta_reg_2;
+	u32 cksta_reg_3;
+	u32 cksta_reg_4;
+	u32 reserved14[20];
+	u32 clk_auddiv_0;	/* 0x0320 */
+	u32 clk_auddiv_1;
+	u32 clk_auddiv_2;
+	u32 aud_top_cfg;
+	u32 aud_top_mon;
+	u32 clk_auddiv_3;
+	u32 clk_auddiv_4;
+};
+
+check_member(mtk_topckgen_regs, clk_cfg_0, 0x0020);
+check_member(mtk_topckgen_regs, clk_extck_reg, 0x0204);
+check_member(mtk_topckgen_regs, clk26cali_0, 0x0218);
+check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x022c);
+check_member(mtk_topckgen_regs, clk_misc_cfg_1, 0x0238);
+check_member(mtk_topckgen_regs, clk_misc_cfg_2, 0x0244);
+check_member(mtk_topckgen_regs, clk_misc_cfg_3, 0x0250);
+check_member(mtk_topckgen_regs, clk_misc_cfg_6, 0x025c);
+check_member(mtk_topckgen_regs, clkmon_clk_sel, 0x029c);
+check_member(mtk_topckgen_regs, cksta_reg_0, 0x02bc);
+check_member(mtk_topckgen_regs, clk_auddiv_0, 0x0320);
+check_member(mtk_topckgen_regs, clk_auddiv_4, 0x0338);
+
+struct mtk_apmixed_regs {
+	u32 ap_pll_con0;
+	u32 ap_pll_con1;
+	u32 ap_pll_con2;
+	u32 ap_pll_con3;
+	u32 ap_pll_con4;
+	u32 ap_pll_con5;
+	u32 clksq_stb_con0;
+	u32 clksq_stb_con1;
+	u32 armpll_ll_con0;
+	u32 armpll_ll_con1;
+	u32 armpll_ll_con2;
+	u32 armpll_ll_con3;
+	u32 ccipll_con0;
+	u32 pll_chg_con0;
+	u32 reserved1[6];
+	u32 pllon_con0;	/* 0x0050 */
+	u32 pllon_con1;
+	u32 pllon_con2;
+	u32 pllon_con3;
+	u32 reserved2[4];
+	u32 armpll_bl_con0;	/* 0x0070 */
+	u32 armpll_bl_con1;
+	u32 armpll_bl_con2;
+	u32 armpll_bl_con3;
+	u32 armpll_bl_con4;
+	u32 reserved3[3];
+	u32 ap_pllgp2_con0;	/* 0x0090 */
+	u32 reserved4[3];
+	u32 tvdpll1_con0;	/* 0x00a0 */
+	u32 tvdpll1_con1;
+	u32 tvdpll1_con2;
+	u32 tvdpll1_con3;
+	u32 tvdpll1_con4;
+	u32 reserved5[3];
+	u32 tvdpll2_con0;	/* 0x00c0 */
+	u32 tvdpll2_con1;
+	u32 tvdpll2_con2;
+	u32 tvdpll2_con3;
+	u32 tvdpll2_con4;
+	u32 reserved6[3];
+	u32 mmpll_con0;	/* 0x00e0 */
+	u32 mmpll_con1;
+	u32 mmpll_con2;
+	u32 mmpll_con3;
+	u32 mmpll_con4;
+	u32 reserved7[3];
+	u32 imgpll_con0;	/* 0x0100 */
+	u32 imgpll_con1;
+	u32 imgpll_con2;
+	u32 imgpll_con3;
+	u32 imgpll_con4;
+	u32 reserved8[3];
+	u32 ap_pllgp3_con0;	/* 0x0120 */
+	u32 reserved9[11];
+	u32 dgipll_con0;	/* 0x0150 */
+	u32 dgipll_con1;
+	u32 dgipll_con2;
+	u32 dgipll_con3;
+	u32 dgipll_con4;
+	u32 reserved10[11];
+	u32 respll_con0;	/* 0x0190 */
+	u32 respll_con1;
+	u32 respll_con2;
+	u32 respll_con3;
+	u32 usb1pll_con0;
+	u32 usb1pll_con1;
+	u32 usb1pll_con2;
+	u32 usb1pll_con3;
+	u32 usb1pll_con4;
+	u32 reserved11[7];
+	u32 mainpll_con0;	/* 0x01d0 */
+	u32 mainpll_con1;
+	u32 mainpll_con2;
+	u32 mainpll_con3;
+	u32 mainpll_con4;
+	u32 reserved12[3];
+	u32 univpll_con0;	/* 0x01f0 */
+	u32 univpll_con1;
+	u32 univpll_con2;
+	u32 univpll_con3;
+	u32 ap_pllgp1_con0;
+	u32 reserved13[43];
+	u32 ulposc1_con0;	/* 0x02b0 */
+	u32 ulposc1_con1;
+	u32 reserved14[2];
+	u32 ulposc2_con0;	/* 0x02c0 */
+	u32 ulposc2_con1;
+	u32 reserved15[22];
+	u32 respll_con4;	/* 0x0320 */
+	u32 reserved16[3];
+	u32 ap_pllgp4_con0;	/* 0x0330 */
+	u32 reserved17[3];
+	u32 mfgpll_con0;	/* 0x0340 */
+	u32 mfgpll_con1;
+	u32 mfgpll_con2;
+	u32 mfgpll_con3;
+	u32 mfgpll_con4;
+	u32 reserved18[3];
+	u32 ethpll_con0;	/* 0x0360 */
+	u32 ethpll_con1;
+	u32 ethpll_con2;
+	u32 ethpll_con3;
+	u32 ethpll_con4;
+	u32 reserved19[7];
+	u32 nnapll_con0;	/* 0x0390 */
+	u32 nnapll_con1;
+	u32 nnapll_con2;
+	u32 nnapll_con3;
+	u32 nnapll_con4;
+	u32 reserved20[39];
+	u32 ap_auxadc_con0;	/* 0x0440 */
+	u32 ap_auxadc_con1;
+	u32 ap_auxadc_con2;
+	u32 ap_auxadc_con3;
+	u32 ap_auxadc_con4;
+	u32 ap_auxadc_con5;
+	u32 reserved21[6];
+	u32 apll1_tuner_con0;	/* 0x0470 */
+	u32 apll2_tuner_con0;
+	u32 apll3_tuner_con0;
+	u32 apll4_tuner_con0;
+	u32 apll5_tuner_con0;
+	u32 reserved22[15];
+	u32 pll_pwr_con0;	/* 0x04c0 */
+	u32 pll_pwr_con1;
+	u32 reserved23[2];
+	u32 pll_iso_con0;	/* 0x04d0 */
+	u32 pll_iso_con1;
+	u32 reserved24[2];
+	u32 pll_stb_con0;	/* 0x04e0 */
+	u32 reserved25[3];
+	u32 div_stb_con0;	/* 0x04f0 */
+	u32 reserved26[3];
+	u32 ap_abist_mon_con0;	/* 0x0500 */
+	u32 ap_abist_mon_con1;
+	u32 ap_abist_mon_con2;
+	u32 ap_abist_mon_con3;
+	u32 occscan_con0;
+	u32 occscan_con1;
+	u32 occscan_con2;
+	u32 occscan_con3;
+	u32 mcu_occscan_con0;
+	u32 mcu_occscan_con1;
+	u32 reserved27[6];
+	u32 cksys_occ_sel0;	/* 0x0540 */
+	u32 cksys_occ_sel1;
+	u32 cksys_occ_sel2;
+	u32 cksys_occ_sel3;
+	u32 cksys_occ_sel4;
+	u32 cksys_occ_sel5;
+	u32 cksys_occ_sel6;
+	u32 cksys_occ_sel7;
+	u32 cksys_occ_tstsel0;
+	u32 cksys_occ_tstsel1;
+	u32 cksys_occ_tstsel2;
+	u32 cksys_occ_tstsel3;
+	u32 cksys_occ_tstsel4;
+	u32 reserved28[3];
+	u32 clkdiv_con0;	/* 0x0580 */
+	u32 clkdiv_con1;
+	u32 rsv_rw0_con4;
+	u32 reserved29[1];
+	u32 rsv_rw0_con0;	/* 0x0590 */
+	u32 rsv_rw0_con1;
+	u32 rsv_rw0_con2;
+	u32 rsv_rw0_con3;
+	u32 rsv_ro_con0;
+	u32 rsv_ro_con1;
+	u32 rsv_ro_con2;
+	u32 rsv_ro_con3;
+	u32 reserved30[20];
+	u32 armpll_ll_con4;	/* 0x0600 */
+	u32 reserved31[12];
+	u32 ccipll_con1;	/* 0x0634 */
+	u32 ccipll_con2;
+	u32 ccipll_con3;
+	u32 ccipll_con4;
+	u32 reserved32[47];
+	u32 univpll_con4;	/* 0x0700 */
+	u32 reserved33[3];
+	u32 msdcpll_con0;	/* 0x0710 */
+	u32 msdcpll_con1;
+	u32 msdcpll_con2;
+	u32 msdcpll_con3;
+	u32 msdcpll_con4;
+	u32 reserved34[7];
+	u32 apll4_con0;	/* 0x0740 */
+	u32 apll4_con1;
+	u32 apll4_con2;
+	u32 apll4_con3;
+	u32 apll4_con4;
+	u32 reserved35[3];
+	u32 apll3_con0;	/* 0x0760 */
+	u32 apll3_con1;
+	u32 apll3_con2;
+	u32 apll3_con3;
+	u32 apll3_con4;
+	u32 reserved36[3];
+	u32 apll2_con0;	/* 0x0780 */
+	u32 apll2_con1;
+	u32 apll2_con2;
+	u32 apll2_con3;
+	u32 apll2_con4;
+	u32 reserved37[3];
+	u32 apll5_con0;	/* 0x07a0 */
+	u32 apll5_con1;
+	u32 apll5_con2;
+	u32 apll5_con3;
+	u32 apll5_con4;
+	u32 reserved38[3];
+	u32 apll1_con0;	/* 0x07c0 */
+	u32 apll1_con1;
+	u32 apll1_con2;
+	u32 apll1_con3;
+	u32 apll1_con4;
+	u32 reserved39[3];
+	u32 adsppll_con0;	/* 0x07e0 */
+	u32 adsppll_con1;
+	u32 adsppll_con2;
+	u32 adsppll_con3;
+	u32 adsppll_con4;
+	u32 reserved40[3];
+	u32 mpll_con0;	/* 0x0800 */
+	u32 mpll_con1;
+	u32 mpll_con2;
+	u32 mpll_con3;
+	u32 mpll_con4;
+	u32 reserved41[23];
+	u32 hdmipll2_con0;	/* 0x0870 */
+	u32 hdmipll2_con1;
+	u32 hdmipll2_con2;
+	u32 hdmipll2_con3;
+	u32 hdmipll2_con4;
+	u32 reserved42[3];
+	u32 vdecpll_con0;	/* 0x0890 */
+	u32 vdecpll_con1;
+	u32 vdecpll_con2;
+	u32 vdecpll_con3;
+	u32 vdecpll_con4;
+	u32 reserved43[7];
+	u32 hdmipll1_con0;	/* 0x08c0 */
+	u32 hdmipll1_con1;
+	u32 hdmipll1_con2;
+	u32 hdmipll1_con3;
+	u32 hdmipll1_con4;
+	u32 reserved44[3];
+	u32 hdmirx_apll_con0;	/* 0x08e0 */
+	u32 hdmirx_apll_con1;
+	u32 hdmirx_apll_con2;
+	u32 hdmirx_apll_con3;
+	u32 hdmirx_apll_con4;
+	u32 reserved45[291];
+	u32 occscan_con4;	/* 0x0d80 */
+	u32 occscan_con5;
+	u32 occscan_con6;
+	u32 occscan_con7;
+	u32 occscan_con8;
+	u32 occscan_con9;
+	u32 occscan_con10;
+	u32 occscan_con11;
+	u32 occscan_con12;
+	u32 occscan_con13;
+	u32 occscan_con14;
+	u32 occscan_con15;
+	u32 ref_clk_con0;
+	u32 reserved46[3];
+	u32 apll1_con5;	/* 0x0dc0 */
+	u32 apll2_con5;
+	u32 apll3_con5;
+	u32 apll4_con5;
+	u32 apll5_con5;
+	u32 hdmirx_apll_con5;
+};
+
+check_member(mtk_apmixed_regs, pllon_con0, 0x0050);
+check_member(mtk_apmixed_regs, armpll_bl_con0, 0x0070);
+check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x0090);
+check_member(mtk_apmixed_regs, tvdpll1_con0, 0x00a0);
+check_member(mtk_apmixed_regs, tvdpll2_con0, 0x00c0);
+check_member(mtk_apmixed_regs, mmpll_con0, 0x00e0);
+check_member(mtk_apmixed_regs, imgpll_con0, 0x0100);
+check_member(mtk_apmixed_regs, ap_pllgp3_con0, 0x0120);
+check_member(mtk_apmixed_regs, dgipll_con0, 0x0150);
+check_member(mtk_apmixed_regs, respll_con0, 0x0190);
+check_member(mtk_apmixed_regs, mainpll_con0, 0x01d0);
+check_member(mtk_apmixed_regs, univpll_con0, 0x01f0);
+check_member(mtk_apmixed_regs, ulposc1_con0, 0x02b0);
+check_member(mtk_apmixed_regs, ulposc2_con0, 0x02c0);
+check_member(mtk_apmixed_regs, respll_con4, 0x0320);
+check_member(mtk_apmixed_regs, ap_pllgp4_con0, 0x0330);
+check_member(mtk_apmixed_regs, mfgpll_con0, 0x0340);
+check_member(mtk_apmixed_regs, ethpll_con0, 0x0360);
+check_member(mtk_apmixed_regs, nnapll_con0, 0x0390);
+check_member(mtk_apmixed_regs, ap_auxadc_con0, 0x0440);
+check_member(mtk_apmixed_regs, apll1_tuner_con0, 0x0470);
+check_member(mtk_apmixed_regs, pll_pwr_con0, 0x04c0);
+check_member(mtk_apmixed_regs, pll_iso_con0, 0x04d0);
+check_member(mtk_apmixed_regs, pll_stb_con0, 0x04e0);
+check_member(mtk_apmixed_regs, div_stb_con0, 0x04f0);
+check_member(mtk_apmixed_regs, ap_abist_mon_con0, 0x0500);
+check_member(mtk_apmixed_regs, cksys_occ_sel0, 0x0540);
+check_member(mtk_apmixed_regs, clkdiv_con0, 0x0580);
+check_member(mtk_apmixed_regs, armpll_ll_con4, 0x0600);
+check_member(mtk_apmixed_regs, ccipll_con1, 0x0634);
+check_member(mtk_apmixed_regs, univpll_con4, 0x0700);
+check_member(mtk_apmixed_regs, msdcpll_con0, 0x0710);
+check_member(mtk_apmixed_regs, apll4_con0, 0x0740);
+check_member(mtk_apmixed_regs, apll3_con0, 0x0760);
+check_member(mtk_apmixed_regs, apll2_con0, 0x0780);
+check_member(mtk_apmixed_regs, apll5_con0, 0x07a0);
+check_member(mtk_apmixed_regs, apll1_con0, 0x07c0);
+check_member(mtk_apmixed_regs, adsppll_con0, 0x07e0);
+check_member(mtk_apmixed_regs, mpll_con0, 0x0800);
+check_member(mtk_apmixed_regs, hdmipll2_con0, 0x0870);
+check_member(mtk_apmixed_regs, vdecpll_con0, 0x0890);
+check_member(mtk_apmixed_regs, hdmipll1_con0, 0x08c0);
+check_member(mtk_apmixed_regs, hdmirx_apll_con0, 0x08e0);
+check_member(mtk_apmixed_regs, occscan_con4, 0x0d80);
+check_member(mtk_apmixed_regs, apll1_con5, 0x0dc0);
+check_member(mtk_apmixed_regs, hdmirx_apll_con5, 0x0dd4);
+
 /* top_div rate */
 enum {
 	CLK26M_HZ	= 26 * MHz,
diff --git a/src/soc/mediatek/mt8195/include/soc/spm.h b/src/soc/mediatek/mt8195/include/soc/spm.h
new file mode 100644
index 0000000000..c90e632477
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/spm.h
@@ -0,0 +1,536 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_SPM_H
+#define SOC_MEDIATEK_MT8195_SPM_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mtk_spm_regs {
+	u32 poweron_config_set;
+	u32 spm_power_on_val0;
+	u32 spm_power_on_val1;
+	u32 spm_clk_con;
+	u32 spm_clk_settle;
+	u32 spm_ap_standby_con;
+	u32 pcm_con0;
+	u32 pcm_con1;
+	u32 spm_power_on_val2;
+	u32 spm_power_on_val3;
+	u32 pcm_reg_data_ini;
+	u32 pcm_pwr_io_en;
+	u32 pcm_timer_val;
+	u32 pcm_wdt_val;
+	u32 rsv_6038[2];
+	u32 spm_sw_rst_con;
+	u32 spm_sw_rst_con_set;
+	u32 spm_sw_rst_con_clr;
+	u32 rsv_604c;
+	u32 spm_arbiter_en;
+	u32 scpsys_clk_con;
+	u32 spm_sram_rsv_con;
+	u32 spm_swint;
+	u32 spm_swint_set;
+	u32 spm_swint_clr;
+	u32 spm_scp_mailbox;
+	u32 scp_spm_mailbox;
+	u32 spm_scp_irq;
+	u32 spm_cpu_wakeup_event;
+	u32 spm_irq_mask;
+	u32 rsv_607c;
+	u32 spm_src_req;
+	u32 spm_src_mask;
+	u32 spm_src2_mask;
+	u32 rsv_608c;
+	u32 spm_src3_mask;
+	u32 spm_src4_mask;
+	u32 spm_wakeup_event_mask2;
+	u32 spm_wakeup_event_mask;
+	u32 spm_wakeup_event_sens;
+	u32 spm_wakeup_event_clear;
+	u32 spm_wakeup_event_ext_mask;
+	u32 scp_clk_con;
+	u32 pcm_debug_con;
+	u32 ddren_dbc_con;
+	u32 spm_resource_ack_con0;
+	u32 spm_resource_ack_con1;
+	u32 spm_resource_ack_con2;
+	u32 spm_resource_ack_con3;
+	u32 spm_resource_ack_con4;
+	u32 spm_sram_con;
+	u32 rsv_60d0[12];
+	u32 pcm_reg0_data;
+	u32 pcm_reg2_data;
+	u32 pcm_reg6_data;
+	u32 pcm_reg7_data;
+	u32 pcm_reg13_data;
+	u32 src_req_sta_0;
+	u32 src_req_sta_1;
+	u32 rsv_611c;
+	u32 src_req_sta_2;
+	u32 src_req_sta_3;
+	u32 src_req_sta_4;
+	u32 rsv_612c;
+	u32 pcm_timer_out;
+	u32 pcm_wdt_out;
+	u32 spm_irq_sta;
+	u32 md32pcm_wakeup_sta;
+	u32 md32pcm_event_sta;
+	u32 spm_wakeup_sta;
+	u32 spm_wakeup_ext_sta;
+	u32 spm_wakeup_misc;
+	u32 mm_dvfs_halt;
+	u32 rsv_6154[4];
+	u32 subsys_idle_sta;
+	u32 pcm_sta;
+	u32 pwr_status;
+	u32 pwr_status_2nd;
+	u32 cpu_pwr_status;
+	u32 cpu_pwr_status_2nd;
+	u32 spm_vtcxo_event_count_sta;
+	u32 spm_infra_event_count_sta;
+	u32 spm_vrf18_event_count_sta;
+	u32 spm_apsrc_event_count_sta;
+	u32 spm_ddren_event_count_sta;
+	u32 md32pcm_sta;
+	u32 md32pcm_pc;
+	u32 other_pwr_status;
+	u32 dvfsrc_event_sta;
+	u32 bus_protect_rdy;
+	u32 bus_protect1_rdy;
+	u32 bus_protect2_rdy;
+	u32 bus_protect3_rdy;
+	u32 bus_protect4_rdy;
+	u32 bus_protect5_rdy;
+	u32 bus_protect6_rdy;
+	u32 bus_protect7_rdy;
+	u32 bus_protect8_rdy;
+	u32 bus_protect9_rdy;
+	u32 rsv_61c8[2];
+	u32 spm_twam_last_sta0;
+	u32 spm_twam_last_sta1;
+	u32 spm_twam_last_sta2;
+	u32 spm_twam_last_sta3;
+	u32 spm_twam_curr_sta0;
+	u32 spm_twam_curr_sta1;
+	u32 spm_twam_curr_sta2;
+	u32 spm_twam_curr_sta3;
+	u32 spm_twam_timer_out;
+	u32 spm_cg_check_sta;
+	u32 spm_dvfs_sta;
+	u32 spm_dvfs_opp_sta;
+	u32 cpueb_pwr_con;
+	u32 spm_mcusys_pwr_con;
+	u32 spm_cputop_pwr_con;
+	u32 spm_cpu0_pwr_con;
+	u32 spm_cpu1_pwr_con;
+	u32 spm_cpu2_pwr_con;
+	u32 spm_cpu3_pwr_con;
+	u32 spm_cpu4_pwr_con;
+	u32 spm_cpu5_pwr_con;
+	u32 spm_cpu6_pwr_con;
+	u32 spm_cpu7_pwr_con;
+	u32 armpll_clk_con;
+	u32 mcusys_idle_sta;
+	u32 gic_wakeup_sta;
+	u32 cpu_spare_con;
+	u32 cpu_spare_con_set;
+	u32 cpu_spare_con_clr;
+	u32 armpll_clk_sel;
+	u32 ext_int_wakeup_req;
+	u32 ext_int_wakeup_req_set;
+	u32 ext_int_wakeup_req_clr;
+	u32 rsv_6254[3];
+	u32 cpu_irq_mask;
+	u32 cpu_irq_mask_set;
+	u32 cpu_irq_mask_clr;
+	u32 rsv_626c[5];
+	u32 cpu_wfi_en;
+	u32 cpu_wfi_en_set;
+	u32 cpu_wfi_en_clr;
+	u32 rsv_628c;
+	u32 sysram_con;
+	u32 sysrom_con;
+	u32 rsv_6298[2];
+	u32 root_cputop_addr;
+	u32 root_core_addr;
+	u32 rsv_62a8[10];
+	u32 spm2sw_mailbox_0;
+	u32 spm2sw_mailbox_1;
+	u32 spm2sw_mailbox_2;
+	u32 spm2sw_mailbox_3;
+	u32 sw2spm_int;
+	u32 sw2spm_int_set;
+	u32 sw2spm_int_clr;
+	u32 sw2spm_mailbox_0;
+	u32 sw2spm_mailbox_1;
+	u32 sw2spm_mailbox_2;
+	u32 sw2spm_mailbox_3;
+	u32 sw2spm_cfg;
+	u32 mfg0_pwr_con;
+	u32 mfg1_pwr_con;
+	u32 mfg2_pwr_con;
+	u32 mfg3_pwr_con;
+	u32 mfg4_pwr_con;
+	u32 mfg5_pwr_con;
+	u32 mfg6_pwr_con;
+	u32 ifr_pwr_con;
+	u32 ifr_sub_pwr_con;
+	u32 peri_pwr_con;
+	u32 pextp_mac_top_p0_pwr_con;
+	u32 pextp_mac_top_p1_pwr_con;
+	u32 pcie_phy_pwr_con;
+	u32 ssusb_pcie_phy_pwr_con;
+	u32 ssusb_top_p1_pwr_con;
+	u32 ssusb_top_p2_pwr_con;
+	u32 ssusb_top_p3_pwr_con;
+	u32 ether_pwr_con;
+	u32 dpy0_pwr_con;
+	u32 dpy1_pwr_con;
+	u32 dpm0_pwr_con;
+	u32 dpm1_pwr_con;
+	u32 audio_pwr_con;
+	u32 audio_asrc_pwr_con;
+	u32 adsp_pwr_con;
+	u32 vppsys0_pwr_con;
+	u32 vppsys1_pwr_con;
+	u32 vdosys0_pwr_con;
+	u32 vdosys1_pwr_con;
+	u32 wpesys_pwr_con;
+	u32 dp_tx_pwr_con;
+	u32 edp_tx_pwr_con;
+	u32 hdmi_tx_pwr_con;
+	u32 hdmi_rx_pwr_con;
+	u32 vde0_pwr_con;
+	u32 vde1_pwr_con;
+	u32 vde2_pwr_con;
+	u32 ven_pwr_con;
+	u32 ven_core1_pwr_con;
+	u32 cam_pwr_con;
+	u32 cam_rawa_pwr_con;
+	u32 cam_rawb_pwr_con;
+	u32 cam_rawc_pwr_con;
+	u32 img_m_pwr_con;
+	u32 img_d_pwr_con;
+	u32 ipe_pwr_con;
+	u32 nna0_pwr_con;
+	u32 nna1_pwr_con;
+	u32 ipnna_pwr_con;
+	u32 csi_rx_top_pwr_con;
+	u32 rsv_63c8;
+	u32 sspm_sram_con;
+	u32 scp_sram_con;
+	u32 ufs_sram_con;
+	u32 devapc_ifr_sram_con;
+	u32 devapc_subifr_sram_con;
+	u32 devapc_acp_sram_con;
+	u32 usb_sram_con;
+	u32 dummy_sram_con;
+	u32 ext_buck_iso;
+	u32 msdc_sram_con;
+	u32 debugtop_sram_con;
+	u32 dpmaif_sram_con;
+	u32 gcpu_sram_con;
+	u32 spm_mem_ck_sel;
+	u32 spm_bus_protect_mask_b;
+	u32 spm_bus_protect1_mask_b;
+	u32 spm_bus_protect2_mask_b;
+	u32 spm_bus_protect3_mask_b;
+	u32 spm_bus_protect4_mask_b;
+	u32 spm_bus_protect5_mask_b;
+	u32 spm_bus_protect6_mask_b;
+	u32 spm_bus_protect7_mask_b;
+	u32 spm_bus_protect8_mask_b;
+	u32 spm_bus_protect9_mask_b;
+	u32 spm_emi_bw_mode;
+	u32 rsv_6430;
+	u32 spm2mm_con;
+	u32 spm2cpueb_con;
+	u32 ap_mdsrc_req;
+	u32 spm2emi_enter_ulpm;
+	u32 spm_pll_con;
+	u32 rc_spm_ctrl;
+	u32 spm_dram_mcu_sw_con_0;
+	u32 spm_dram_mcu_sw_con_1;
+	u32 spm_dram_mcu_sw_con_2;
+	u32 spm_dram_mcu_sw_con_3;
+	u32 spm_dram_mcu_sw_con_4;
+	u32 spm_dram_mcu_sta_0;
+	u32 spm_dram_mcu_sta_1;
+	u32 spm_dram_mcu_sta_2;
+	u32 spm_dram_mcu_sw_sel_0;
+	u32 relay_dvfs_level;
+	u32 dramc_dpy_clk_sw_con_0;
+	u32 dramc_dpy_clk_sw_con_1;
+	u32 dramc_dpy_clk_sw_con_2;
+	u32 dramc_dpy_clk_sw_con_3;
+	u32 dramc_dpy_clk_sw_sel_0;
+	u32 dramc_dpy_clk_sw_sel_1;
+	u32 dramc_dpy_clk_sw_sel_2;
+	u32 dramc_dpy_clk_sw_sel_3;
+	u32 dramc_dpy_clk_spm_con;
+	u32 spm_dvfs_level;
+	u32 spm_cirq_con;
+	u32 spm_dvfs_misc;
+	u32 rg_module_sw_cg_0_mask_req_0;
+	u32 rg_module_sw_cg_0_mask_req_1;
+	u32 rg_module_sw_cg_0_mask_req_2;
+	u32 rg_module_sw_cg_1_mask_req_0;
+	u32 rg_module_sw_cg_1_mask_req_1;
+	u32 rg_module_sw_cg_1_mask_req_2;
+	u32 rg_module_sw_cg_2_mask_req_0;
+	u32 rg_module_sw_cg_2_mask_req_1;
+	u32 rg_module_sw_cg_2_mask_req_2;
+	u32 rg_module_sw_cg_3_mask_req_0;
+	u32 rg_module_sw_cg_3_mask_req_1;
+	u32 rg_module_sw_cg_3_mask_req_2;
+	u32 pwr_status_mask_req_0;
+	u32 pwr_status_mask_req_1;
+	u32 pwr_status_mask_req_2;
+	u32 spm_cg_check_con;
+	u32 spm_src_rdy_sta;
+	u32 spm_dvs_dfs_level;
+	u32 spm_force_dvfs;
+	u32 dramc_mcu_sram_con;
+	u32 dramc_mcu2_sram_con;
+	u32 dpy_shu_sram_con;
+	u32 dpy_shu2_sram_con;
+	u32 rsv_6500[64];
+	u32 spm_sw_flag_0;
+	u32 spm_sw_debug_0;
+	u32 spm_sw_flag_1;
+	u32 spm_sw_debug_1;
+	u32 spm_sw_rsv_0;
+	u32 spm_sw_rsv_1;
+	u32 spm_sw_rsv_2;
+	u32 spm_sw_rsv_3;
+	u32 spm_sw_rsv_4;
+	u32 spm_sw_rsv_5;
+	u32 spm_sw_rsv_6;
+	u32 spm_sw_rsv_7;
+	u32 spm_sw_rsv_8;
+	u32 spm_bk_wake_event;
+	u32 spm_bk_vtcxo_dur;
+	u32 spm_bk_wake_misc;
+	u32 spm_bk_pcm_timer;
+	u32 ulposc_con;
+	u32 rsv_6648[2];
+	u32 spm_rsv_con_0;
+	u32 spm_rsv_con_1;
+	u32 spm_rsv_sta_0;
+	u32 spm_rsv_sta_1;
+	u32 spm_spare_con;
+	u32 spm_spare_con_set;
+	u32 spm_spare_con_clr;
+	u32 spm_cross_wake_m00_req;
+	u32 spm_cross_wake_m01_req;
+	u32 spm_cross_wake_m02_req;
+	u32 spm_cross_wake_m03_req;
+	u32 scp_vcore_level;
+	u32 sc_mm_ck_sel_con;
+	u32 spare_ack_mask;
+	u32 rsv_6688;
+	u32 spm_dv_con_0;
+	u32 spm_dv_con_1;
+	u32 spm_dv_sta;
+	u32 conn_xowcn_debug_en;
+	u32 spm_sema_m0;
+	u32 spm_sema_m1;
+	u32 spm_sema_m2;
+	u32 spm_sema_m3;
+	u32 spm_sema_m4;
+	u32 spm_sema_m5;
+	u32 spm_sema_m6;
+	u32 spm_sema_m7;
+	u32 spm2adsp_mailbox;
+	u32 adsp2spm_mailbox;
+	u32 spm_adsp_irq;
+	u32 spm_md32_irq;
+	u32 spm2pmcu_mailbox_0;
+	u32 spm2pmcu_mailbox_1;
+	u32 spm2pmcu_mailbox_2;
+	u32 spm2pmcu_mailbox_3;
+	u32 pmcu2spm_mailbox_0;
+	u32 pmcu2spm_mailbox_1;
+	u32 pmcu2spm_mailbox_2;
+	u32 pmcu2spm_mailbox_3;
+	u32 ufs_psri_sw;
+	u32 ufs_psri_sw_set;
+	u32 ufs_psri_sw_clr;
+	u32 spm_ap_sema;
+	u32 spm_spm_sema;
+	u32 spm_dvfs_con;
+	u32 spm_dvfs_con_sta;
+	u32 spm_pmic_spmi_con;
+	u32 rsv_670c;
+	u32 spm_dvfs_cmd0;
+	u32 spm_dvfs_cmd1;
+	u32 spm_dvfs_cmd2;
+	u32 spm_dvfs_cmd3;
+	u32 spm_dvfs_cmd4;
+	u32 spm_dvfs_cmd5;
+	u32 spm_dvfs_cmd6;
+	u32 spm_dvfs_cmd7;
+	u32 spm_dvfs_cmd8;
+	u32 spm_dvfs_cmd9;
+	u32 spm_dvfs_cmd10;
+	u32 spm_dvfs_cmd11;
+	u32 spm_dvfs_cmd12;
+	u32 spm_dvfs_cmd13;
+	u32 spm_dvfs_cmd14;
+	u32 spm_dvfs_cmd15;
+	u32 spm_dvfs_cmd16;
+	u32 spm_dvfs_cmd17;
+	u32 spm_dvfs_cmd18;
+	u32 spm_dvfs_cmd19;
+	u32 spm_dvfs_cmd20;
+	u32 spm_dvfs_cmd21;
+	u32 spm_dvfs_cmd22;
+	u32 spm_dvfs_cmd23;
+	u32 sys_timer_value_l;
+	u32 sys_timer_value_h;
+	u32 sys_timer_start_l;
+	u32 sys_timer_start_h;
+	u32 sys_timer_latch_l_00;
+	u32 sys_timer_latch_h_00;
+	u32 sys_timer_latch_l_01;
+	u32 sys_timer_latch_h_01;
+	u32 sys_timer_latch_l_02;
+	u32 sys_timer_latch_h_02;
+	u32 sys_timer_latch_l_03;
+	u32 sys_timer_latch_h_03;
+	u32 sys_timer_latch_l_04;
+	u32 sys_timer_latch_h_04;
+	u32 sys_timer_latch_l_05;
+	u32 sys_timer_latch_h_05;
+	u32 sys_timer_latch_l_06;
+	u32 sys_timer_latch_h_06;
+	u32 sys_timer_latch_l_07;
+	u32 sys_timer_latch_h_07;
+	u32 sys_timer_latch_l_08;
+	u32 sys_timer_latch_h_08;
+	u32 sys_timer_latch_l_09;
+	u32 sys_timer_latch_h_09;
+	u32 sys_timer_latch_l_10;
+	u32 sys_timer_latch_h_10;
+	u32 sys_timer_latch_l_11;
+	u32 sys_timer_latch_h_11;
+	u32 sys_timer_latch_l_12;
+	u32 sys_timer_latch_h_12;
+	u32 sys_timer_latch_l_13;
+	u32 sys_timer_latch_h_13;
+	u32 sys_timer_latch_l_14;
+	u32 sys_timer_latch_h_14;
+	u32 sys_timer_latch_l_15;
+	u32 sys_timer_latch_h_15;
+	u32 pcm_wdt_latch_0;
+	u32 pcm_wdt_latch_1;
+	u32 pcm_wdt_latch_2;
+	u32 pcm_wdt_latch_3;
+	u32 pcm_wdt_latch_4;
+	u32 pcm_wdt_latch_5;
+	u32 pcm_wdt_latch_6;
+	u32 pcm_wdt_latch_7;
+	u32 pcm_wdt_latch_8;
+	u32 pcm_wdt_latch_9;
+	u32 pcm_wdt_latch_10;
+	u32 pcm_wdt_latch_11;
+	u32 pcm_wdt_latch_12;
+	u32 pcm_wdt_latch_13;
+	u32 pcm_wdt_latch_14;
+	u32 pcm_wdt_latch_15;
+	u32 pcm_wdt_latch_16;
+	u32 pcm_wdt_latch_17;
+	u32 pcm_wdt_latch_18;
+	u32 pcm_wdt_latch_spare_0;
+	u32 pcm_wdt_latch_spare_1;
+	u32 pcm_wdt_latch_spare_2;
+	u32 rsv_6858[18];
+	u32 dramc_gating_err_latch_ch0_0;
+	u32 dramc_gating_err_latch_ch0_1;
+	u32 dramc_gating_err_latch_ch0_2;
+	u32 dramc_gating_err_latch_ch0_3;
+	u32 dramc_gating_err_latch_ch0_4;
+	u32 dramc_gating_err_latch_ch0_5;
+	u32 rsv_68b8[15];
+	u32 dramc_gating_err_latch_spare_0;
+	u32 rsv_68f8[2];
+	u32 spm_ack_chk_con_0;
+	u32 spm_ack_chk_pc_0;
+	u32 spm_ack_chk_sel_0;
+	u32 spm_ack_chk_timer_0;
+	u32 spm_ack_chk_sta_0;
+	u32 spm_ack_chk_swint_0;
+	u32 rsv_6918[2];
+	u32 spm_ack_chk_con_1;
+	u32 spm_ack_chk_pc_1;
+	u32 spm_ack_chk_sel_1;
+	u32 spm_ack_chk_timer_1;
+	u32 spm_ack_chk_sta_1;
+	u32 spm_ack_chk_swint_1;
+	u32 rsv_6938[2];
+	u32 spm_ack_chk_con_2;
+	u32 spm_ack_chk_pc_2;
+	u32 spm_ack_chk_sel_2;
+	u32 spm_ack_chk_timer_2;
+	u32 spm_ack_chk_sta_2;
+	u32 spm_ack_chk_swint_2;
+	u32 rsv_6958[2];
+	u32 spm_ack_chk_con_3;
+	u32 spm_ack_chk_pc_3;
+	u32 spm_ack_chk_sel_3;
+	u32 spm_ack_chk_timer_3;
+	u32 spm_ack_chk_sta_3;
+	u32 spm_ack_chk_swint_3;
+	u32 spm_counter_0;
+	u32 spm_counter_1;
+	u32 spm_counter_2;
+	u32 rsv_6984[2];
+	u32 sys_timer_con;
+	u32 spm_twam_con;
+	u32 spm_twam_window_len;
+	u32 spm_twam_idle_sel;
+	u32 spm_twam_event_clear;
+	u32 rsv_69a0[344];
+	u32 pmsr_last_dat;
+	u32 pmsr_last_cnt;
+	u32 pmsr_last_ack;
+	u32 rsv_6f0c;
+	u32 spm_pmsr_sel_con0;
+	u32 spm_pmsr_sel_con1;
+	u32 spm_pmsr_sel_con2;
+	u32 spm_pmsr_sel_con3;
+	u32 spm_pmsr_sel_con4;
+	u32 spm_pmsr_sel_con5;
+	u32 spm_pmsr_sel_con6;
+	u32 spm_pmsr_sel_con7;
+	u32 spm_pmsr_sel_con8;
+	u32 spm_pmsr_sel_con9;
+	u32 rsv_6f38;
+	u32 spm_pmsr_sel_con10;
+	u32 spm_pmsr_sel_con11;
+	u32 rsv_6f44[29];
+	u32 spm_pmsr_tiemr_sta0;
+	u32 spm_pmsr_tiemr_sta1;
+	u32 spm_pmsr_tiemr_sta2;
+	u32 spm_pmsr_general_con0;
+	u32 spm_pmsr_general_con1;
+	u32 spm_pmsr_general_con2;
+	u32 spm_pmsr_general_con3;
+	u32 spm_pmsr_general_con4;
+	u32 spm_pmsr_general_con5;
+	u32 spm_pmsr_sw_reset;
+	u32 spm_pmsr_mon_con0;
+	u32 spm_pmsr_mon_con1;
+	u32 spm_pmsr_mon_con2;
+	u32 spm_pmsr_len_con0;
+	u32 spm_pmsr_len_con1;
+	u32 spm_pmsr_len_con2;
+};
+
+check_member(mtk_spm_regs, ap_mdsrc_req, 0x043c);
+check_member(mtk_spm_regs, ulposc_con, 0x644);
+
+static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
+
+#endif  /* SOC_MEDIATEK_MT8195_SPM_H */