diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2021-07-14 15:39:40 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-10 15:17:47 +0000 |
| commit | ac1410d25f801b927bec096c165c291c6aa43816 (patch) | |
| tree | ecd7a2ef52bf56e43a572bd08e527d11c9583a1e /src/soc/mediatek/mt8195/include | |
| parent | 31b20a1277db9d05129dea2599243553b19a67c6 (diff) | |
soc/mediatek/mt8195: Add driver to configure PCIe
Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early
stage to reduce the impact of 100ms delay.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6799c53b03a33be91157ea088d829beb4272976
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8195/include')
| -rw-r--r-- | src/soc/mediatek/mt8195/include/soc/pcie.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/include/soc/pcie.h b/src/soc/mediatek/mt8195/include/soc/pcie.h new file mode 100644 index 0000000000..0978531645 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/pcie.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_PCIE_H +#define SOC_MEDIATEK_MT8195_PCIE_H + +#include <soc/pcie_common.h> + +void mtk_pcie_pre_init(void); +void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl); + +#endif |