From ac1410d25f801b927bec096c165c291c6aa43816 Mon Sep 17 00:00:00 2001 From: Jianjun Wang Date: Wed, 14 Jul 2021 15:39:40 +0800 Subject: soc/mediatek/mt8195: Add driver to configure PCIe Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early stage to reduce the impact of 100ms delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56792 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8195/include/soc/pcie.h | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 src/soc/mediatek/mt8195/include/soc/pcie.h (limited to 'src/soc/mediatek/mt8195/include') diff --git a/src/soc/mediatek/mt8195/include/soc/pcie.h b/src/soc/mediatek/mt8195/include/soc/pcie.h new file mode 100644 index 0000000000..0978531645 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/pcie.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_PCIE_H +#define SOC_MEDIATEK_MT8195_PCIE_H + +#include + +void mtk_pcie_pre_init(void); +void mtk_pcie_get_hw_info(struct mtk_pcie_controller *ctrl); + +#endif -- cgit v1.2.3