diff options
| author | mtk15698 <michael.kao@mediatek.com> | 2020-08-21 17:25:49 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-16 06:28:01 +0000 |
| commit | 70ba37c54f0626a7d596901ab1ecc7c2ff9a891b (patch) | |
| tree | 0d583568a15cd4254a01f3e46c92c9a6691a6fb7 /src/soc/mediatek/mt8192 | |
| parent | 1985894e74711934018f97d082f0b9a9db230894 (diff) | |
soc/mediatek/mt8192: Enable DCM
Enable DCM settings.
Change-Id: I5528d176b6bb1f9a5960de981766235510e6ebf1
Signed-off-by: mtk15698 <michael.kao@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8192')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/pll.h | 49 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/pll.c | 28 |
2 files changed, 77 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 09c4c47118..170196b035 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -306,4 +306,53 @@ DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) +enum { + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK = (0x1f << 12) | (0x1 << 17) | (0x1 << 18), + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON = (0x10 << 12) | (0x1 << 17) | (0x0 << 18), + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK = (0x1 << 0) | + (0x1 << 1) | + (0x1 << 3) | + (0x1 << 4) | + (0x1f << 5) | + (0x1f << 10) | + (0x1 << 20) | + (0x1 << 23) | + (0x1 << 30), + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON = (0x1 << 0) | + (0x1 << 1) | + (0x0 << 3) | + (0x0 << 4) | + (0x10 << 5) | + (0x1 << 10) | + (0x1 << 20) | + (0x1 << 23) | + (0x1 << 30), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK = (0x1 << 8), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON = (0x1 << 8), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK = (0x1 << 8), + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON = (0x0 << 8), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK = (0xf << 0), + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON = (0x0 << 0), + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK = (0x1 << 0) | + (0x1 << 1) | + (0x1 << 3) | + (0x1 << 4) | + (0x1f << 5) | + (0x1f << 10) | + (0x1f << 15) | + (0x1 << 20) | + (0x1 << 21), + INFRACFG_AO_PERI_BUS_DCM_REG0_ON = (0x1 << 0) | + (0x1 << 1) | + (0x0 << 3) | + (0x0 << 4) | + (0x1f << 5) | + (0x0 << 10) | + (0x1f << 15) | + (0x1 << 20) | + (0x1 << 21), + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK = (0x1 << 29) | (0x1 << 31), + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON = (0x1 << 29) | (0x1 << 31), +}; + #endif /* SOC_MEDIATEK_MT8192_PLL_H */ diff --git a/src/soc/mediatek/mt8192/pll.c b/src/soc/mediatek/mt8192/pll.c index 24cfafd8d6..afa7c85e02 100644 --- a/src/soc/mediatek/mt8192/pll.c +++ b/src/soc/mediatek/mt8192/pll.c @@ -427,6 +427,34 @@ void mt_pll_init(void) /* enable infrasys DCM */ setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21); + /* dcm_infracfg_ao_aximem_bus_dcm */ + clrsetbits32(&mt8192_infracfg->infra_aximem_idle_bit_en_0, + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_MASK, + INFRACFG_AO_AXIMEM_BUS_DCM_REG0_ON); + /* dcm_infracfg_ao_infra_bus_dcm */ + clrsetbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, + INFRACFG_AO_INFRA_BUS_DCM_REG0_MASK, + INFRACFG_AO_INFRA_BUS_DCM_REG0_ON); + /* dcm_infracfg_ao_infra_conn_bus_dcm */ + clrsetbits32(&mt8192_infracfg->module_sw_cg_2_set, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_MASK, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG0_ON); + clrsetbits32(&mt8192_infracfg->module_sw_cg_2_clr, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_MASK, + INFRACFG_AO_INFRA_CONN_BUS_DCM_REG1_ON); + /* dcm_infracfg_ao_infra_rx_p2p_dcm */ + clrsetbits32(&mt8192_infracfg->p2p_rx_clk_on, + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_MASK, + INFRACFG_AO_INFRA_RX_P2P_DCM_REG0_ON); + /* dcm_infracfg_ao_peri_bus_dcm */ + clrsetbits32(&mt8192_infracfg->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_BUS_DCM_REG0_MASK, + INFRACFG_AO_PERI_BUS_DCM_REG0_ON); + /* dcm_infracfg_ao_peri_module_dcm */ + clrsetbits32(&mt8192_infracfg->peri_bus_dcm_ctrl, + INFRACFG_AO_PERI_MODULE_DCM_REG0_MASK, + INFRACFG_AO_PERI_MODULE_DCM_REG0_ON); + /* initialize SPM request */ setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff); clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3); |