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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-02 23:48:35 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-04 00:10:20 +0000 |
| commit | c0dbd4cb562b6c2d569eeb12562bfa3eb27925c9 (patch) | |
| tree | 711de2ed198e253a2106ea5020b11a64b21e164e /src/soc/mediatek/mt8192/ufs.c | |
| parent | 404aea866ce60af9f8756f0698dcd8293c0e81bf (diff) | |
soc/amd/picasso: set GPE0_LIMIT to 32 and move definitions to registers
Picasso has 32 configurable GPEs, not only 28.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/ufs.c')
0 files changed, 0 insertions, 0 deletions