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| author | Kevin Chiu <kevin.chiu.17802@gmail.com> | 2021-12-22 11:58:55 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-23 20:47:14 +0000 |
| commit | 4bf08cfbfe5a07a69715f727d571fa7870640f2e (patch) | |
| tree | fea65f9c8ee6ea2b102bf13e2b0bdf500a7a2017 /src/soc/mediatek/mt8192/pll.c | |
| parent | a9796ce010efe31172eaa9677fd7ad1de313a257 (diff) | |
mb/google/brya/var/vell: Add Hynix LP5 DRAM support
Add Hynix H9JCNNNCP3MLYR-N6E LP5 DRAM part for vell:
DRAM Part Name ID to assign
H9JCNNNCP3MLYR-N6E 1 (0001)
BUG=b:204284866
TEST=emerge-brya coreboot
Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/pll.c')
0 files changed, 0 insertions, 0 deletions