diff options
| author | Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> | 2021-04-11 15:28:20 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-10 01:57:49 +0000 |
| commit | 6a6e58cb4197b96f8363a000a66ca54fc3344ddd (patch) | |
| tree | ca8f82cbf45a90becb4358331552d66c142349c2 /src/soc/mediatek/mt8192/include | |
| parent | 24c6355741e9f68fb2304be0dcdadfb25570b787 (diff) | |
soc/mediatek/mt8195: Add clk_buf driver
Both mt8192 and mt8195 use mt6359p clk_buf.
But mt8195 clk_buf uses legacy co-clock mode without srclken_rc.
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/clkbuf.h | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/clkbuf.h b/src/soc/mediatek/mt8192/include/soc/clkbuf.h deleted file mode 100644 index b5fa3a3f1b..0000000000 --- a/src/soc/mediatek/mt8192/include/soc/clkbuf.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef SOC_MEDIATEK_MT8192_CLKBUF_H -#define SOC_MEDIATEK_MT8192_CLKBUF_H - -#include <device/mmio.h> - -enum { - PMIC_RG_DCXO_CW00 = 0x0788, - PMIC_RG_DCXO_CW02 = 0x0790, - PMIC_RG_DCXO_CW08 = 0x079C, - PMIC_RG_DCXO_CW09 = 0x079E, - PMIC_RG_DCXO_CW09_CLR = 0x07A2, - PMIC_RG_DCXO_CW10 = 0x07A4, - PMIC_RG_DCXO_CW12 = 0x07A8, - PMIC_RG_DCXO_CW13 = 0x07AA, - PMIC_RG_DCXO_CW15 = 0x07AE, - PMIC_RG_DCXO_CW19 = 0x07B6, -}; - -enum { - PMIC_TOP_TMA_KEY = 0x3A8, - PMIC_RG_TOP_SPI_CON1 = 0x458, -}; - -enum { - PMIC_TOP_TMA_KEY_UNLOCK = 0x9CA6, -}; - -enum { - PMIC_RG_LDO_VRFCK_ELR = 0x1B40, - PMIC_RG_LDO_VRFCK_CON0 = 0x1D1C, - PMIC_RG_LDO_VRFCK_OP_EN = 0x1D22, - PMIC_RG_LDO_VRFCK_OP_EN_SET = 0x1D24, - PMIC_RG_LDO_VBBCK_CON0 = 0x1D2E, - PMIC_RG_LDO_VBBCK_OP_EN = 0x1D34, - PMIC_RG_LDO_VBBCK_OP_EN_SET = 0x1D36, -}; - -enum { - PMIC_RG_DCXO_ADLDO_BIAS_ELR_0 = 0x209C, - PMIC_RG_DCXO_ADLDO_BIAS_ELR_1 = 0x209E, -}; - -enum { - PMIC_RG_XO_BUF_CTL0 = 0x54C, - PMIC_RG_XO_BUF_CTL1 = 0x54E, - PMIC_RG_XO_BUF_CTL2 = 0x550, - PMIC_RG_XO_BUF_CTL3 = 0x552, - PMIC_RG_XO_BUF_CTL4 = 0x554, - PMIC_RG_XO_CONN_BT0 = 0x556, -}; - -DEFINE_BITFIELD(PMIC_REG_COMMON, 15, 0) -DEFINE_BIT(PMIC_RG_VRFCK_HV_EN, 9) -DEFINE_BIT(PMIC_RG_LDO_VRFCK_EN, 0) -DEFINE_BIT(PMIC_RG_LDO_VRFCK_ANA_SEL, 0) -DEFINE_BIT(PMIC_RG_LDO_VBBCK_EN, 0) -DEFINE_BIT(PMIC_RG_VRFCK_NDIS_EN, 11) -DEFINE_BIT(PMIC_RG_VRFCK_1_NDIS_EN, 0) -DEFINE_BIT(PMIC_RG_LDO_VRFCK_HW14_OP_EN, 14) -DEFINE_BIT(PMIC_RG_LDO_VBBCK_HW14_OP_EN, 14) -DEFINE_BIT(PMIC_RG_SRCLKEN_IN3_EN, 0) -DEFINE_BIT(PMIC_RG_XO_PMIC_TOP_DIG_SW, 2) -DEFINE_BITFIELD(PMIC_RG_XO_VOTE, 10, 0) - -int clk_buf_init(void); - -#endif /* SOC_MEDIATEK_MT8192_CLKBUF_H */ |