diff options
| author | Weiyi Lu <weiyi.lu@mediatek.com> | 2020-06-22 16:21:58 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-10-09 15:33:00 +0000 |
| commit | 26d16527152f6ed93f580c26fb5ead3bdb4117f5 (patch) | |
| tree | 661a672d652f82dbd467cd40400c40f3ea7d87b9 /src/soc/mediatek/mt8192/include | |
| parent | 30b854dccd1fce2d439fb70ffa15064130cad73c (diff) | |
soc/mediatek: Add function to measure clock frequency of MT8192
Implement mt_fmeter_get_freq_khz() in MT8192 to measure frequency of
some pre-defined clocks by frequency meter.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: I75df0b040ed7ea73d25724a3c80040f4e731118f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45402
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/pll.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/pll.h b/src/soc/mediatek/mt8192/include/soc/pll.h index 43c2528994..d5a9cf9a3e 100644 --- a/src/soc/mediatek/mt8192/include/soc/pll.h +++ b/src/soc/mediatek/mt8192/include/soc/pll.h @@ -295,4 +295,11 @@ enum { DEFINE_BITFIELD(PLLGP1_LVRREF, 18, 17) DEFINE_BITFIELD(PLLGP2_LVRREF, 10, 9) +DEFINE_BITFIELD(CLK_DBG_CFG_ABIST_CK_SEL, 21, 16) +DEFINE_BITFIELD(CLK_DBG_CFG_CKGEN_CK_SEL, 13, 8) +DEFINE_BITFIELD(CLK_DBG_CFG_METER_CK_SEL, 1, 0) +DEFINE_BITFIELD(CLK_MISC_CFG_0_METER_DIV, 31, 24) +DEFINE_BITFIELD(CLK26CALI_0_TRIGGER, 4, 4) +DEFINE_BITFIELD(CLK26CALI_1_LOAD_CNT, 25, 16) + #endif /* SOC_MEDIATEK_MT8192_PLL_H */ |