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authorZhanyong Wang <zhanyong.wang@mediatek.com>2020-05-14 13:27:03 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-10-12 08:55:53 +0000
commit06639f2abf86bd0eef9c7808b7e724450d1408b8 (patch)
tree26201f0c284e772f312dcb55f0e4ea04490fecea /src/soc/mediatek/mt8192/include
parent5acea15d63e821a1bc416d206162ed030cd5d57c (diff)
soc/mediatek/mt8192: Refactor USB code among similar SoCs
Adjust ssusb register layout and offset accroding mt8192 Soc then refactor USB code which will be reused among similar SoCs Signed-off-by: Tianping Fang <tianping.fang@mediatek.com> Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com> Change-Id: Icb4cc304654b5fb7cf20b96ab83a22663bfeab63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
-rw-r--r--src/soc/mediatek/mt8192/include/soc/usb.h24
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/usb.h b/src/soc/mediatek/mt8192/include/soc/usb.h
new file mode 100644
index 0000000000..c988270e4b
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/usb.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_USB_H
+#define SOC_MEDIATEK_MT8192_USB_H
+
+#include <soc/usb_common.h>
+
+struct ssusb_sif_port {
+ struct sif_u2_phy_com u2phy;
+ u32 reserved0[64*5];
+ struct sif_u3phyd u3phyd;
+ u32 reserved1[64];
+ struct sif_u3phya u3phya;
+ struct sif_u3phya_da u3phya_da;
+ u32 reserved2[64 * 3];
+};
+check_member(ssusb_sif_port, u3phyd, 0x600);
+check_member(ssusb_sif_port, u3phya, 0x800);
+check_member(ssusb_sif_port, u3phya_da, 0x900);
+check_member(ssusb_sif_port, reserved2, 0xa00);
+
+#define USB_PORT_NUMBER 2
+
+#endif