From 06639f2abf86bd0eef9c7808b7e724450d1408b8 Mon Sep 17 00:00:00 2001 From: Zhanyong Wang Date: Thu, 14 May 2020 13:27:03 +0800 Subject: soc/mediatek/mt8192: Refactor USB code among similar SoCs Adjust ssusb register layout and offset accroding mt8192 Soc then refactor USB code which will be reused among similar SoCs Signed-off-by: Tianping Fang Signed-off-by: Zhanyong Wang Change-Id: Icb4cc304654b5fb7cf20b96ab83a22663bfeab63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45396 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/soc/mediatek/mt8192/include/soc/usb.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 src/soc/mediatek/mt8192/include/soc/usb.h (limited to 'src/soc/mediatek/mt8192/include') diff --git a/src/soc/mediatek/mt8192/include/soc/usb.h b/src/soc/mediatek/mt8192/include/soc/usb.h new file mode 100644 index 0000000000..c988270e4b --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/usb.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_USB_H +#define SOC_MEDIATEK_MT8192_USB_H + +#include + +struct ssusb_sif_port { + struct sif_u2_phy_com u2phy; + u32 reserved0[64*5]; + struct sif_u3phyd u3phyd; + u32 reserved1[64]; + struct sif_u3phya u3phya; + struct sif_u3phya_da u3phya_da; + u32 reserved2[64 * 3]; +}; +check_member(ssusb_sif_port, u3phyd, 0x600); +check_member(ssusb_sif_port, u3phya, 0x800); +check_member(ssusb_sif_port, u3phya_da, 0x900); +check_member(ssusb_sif_port, reserved2, 0xa00); + +#define USB_PORT_NUMBER 2 + +#endif -- cgit v1.2.3