diff options
| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-06-23 14:28:32 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-31 03:07:37 +0000 |
| commit | 2d0117e2fe424f613bb3f3d156099d67bbe0515d (patch) | |
| tree | 6254bada056fb4d8ba17882b869c93c33fd30d67 /src/soc/mediatek/mt8192/include | |
| parent | 4cb885e5be06bc07624a00d33ef4cc1966344255 (diff) | |
soc/mediatek/mt8192: Add dramc 8 phase calibration
To get better PI linearity, perform 8 phase calibration to do
MCK 0/180/45 training and select the best PI settings.
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h index 5a2583cb7f..2dee0445c3 100644 --- a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h @@ -34,6 +34,8 @@ #define REG_SHU_OFFSET_WIDTH 0x700 #define SHU_OFFSET (REG_SHU_OFFSET_WIDTH / 4) +#define DQS_LEVEL_UNKNOWN 0xff + typedef enum { DDRFREQ_400, DDRFREQ_600, |