From 2d0117e2fe424f613bb3f3d156099d67bbe0515d Mon Sep 17 00:00:00 2001 From: Huayang Duan Date: Tue, 23 Jun 2020 14:28:32 +0800 Subject: soc/mediatek/mt8192: Add dramc 8 phase calibration To get better PI linearity, perform 8 phase calibration to do MCK 0/180/45 training and select the best PI settings. Signed-off-by: Huayang Duan Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44709 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu --- src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/soc/mediatek/mt8192/include') diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h index 5a2583cb7f..2dee0445c3 100644 --- a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h @@ -34,6 +34,8 @@ #define REG_SHU_OFFSET_WIDTH 0x700 #define SHU_OFFSET (REG_SHU_OFFSET_WIDTH / 4) +#define DQS_LEVEL_UNKNOWN 0xff + typedef enum { DDRFREQ_400, DDRFREQ_600, -- cgit v1.2.3