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authorSridhar Siricilla <sridhar.siricilla@intel.com>2022-08-15 21:10:58 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-08-17 19:45:41 +0000
commitc760e41a414d2c1aec31982530944bae62c828f0 (patch)
treecb036d063d2d40d1205c7c0bf4c2d252739a08b2 /src/soc/mediatek/mt8192/apusys.c
parent957fde633b6ed1fd698018b1d34c01ebbc6d4178 (diff)
soc/intel/common: Update the comments for CSE RX and TX functions
The patch updates the comments on return values and heci_reset() triggering during error scenarios of heci_receive() and heci_send() functions to reflect the current implementation. Test=Build the code for Gimble Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6c6c3312602c772147cb315db9ea1753d84a0fb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/mediatek/mt8192/apusys.c')
0 files changed, 0 insertions, 0 deletions