diff options
| author | Liya Li <ot_liya.li@mediatek.corp-partner.google.com> | 2022-07-23 14:23:04 +0800 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-29 15:05:48 +0000 |
| commit | 0d13e80852832368ac7ed51f8d04011a71ddbbc2 (patch) | |
| tree | 148e4ac63273f56f2e5bc769908e76b5cc7d21fd /src/soc/mediatek/mt8188/include | |
| parent | 00324b20e102f9f0f040077b584da12ba3fd699c (diff) | |
soc/mediatek/mt8188: Add SPI support
The gpios and the tick delay register are different between MT8188
and previous MediaTek SoCs, so we need to add this patch to support
SPI.
TEST=build pass
BUG=b:236331724
Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com>
Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8188/include')
| -rw-r--r-- | src/soc/mediatek/mt8188/include/soc/spi.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8188/include/soc/spi.h b/src/soc/mediatek/mt8188/include/soc/spi.h index 53aba25243..50ab6127b2 100644 --- a/src/soc/mediatek/mt8188/include/soc/spi.h +++ b/src/soc/mediatek/mt8188/include/soc/spi.h @@ -8,8 +8,23 @@ #ifndef MTK_MT8188_SPI_H #define MTK_MT8188_SPI_H +#include <soc/spi_common.h> #include <spi-generic.h> +#define SPI_BUS_NUMBER 6 + +#define GET_SCK_REG(x) x->spi_cfg2_reg +#define GET_TICK_DLY_REG(x) x->spi_cmd_reg + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 32, 16) +DEFINE_BITFIELD(SPI_TICK_DLY, 24, 22) + void mtk_snfc_init(void); #endif |