diff options
| author | Sen Chu <sen.chu@mediatek.corp-partner.google.com> | 2022-10-18 14:02:14 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-21 14:56:32 +0000 |
| commit | 122b45be6e6cca0ded8c9df65cefe6043b4fcb88 (patch) | |
| tree | fa8457bfc834efb0ea14a08326499ae8e2d07adf /src/soc/mediatek/mt8186/pmif_spmi.c | |
| parent | 28dceaec717111ae49383ecc8678bcef424cda14 (diff) | |
soc/mediatek/mt8186: Add support for PMIC MT6315
On MT8186T, the big cores are powered on by MT6315 via PMIF. This
patch adds the following changes.
- Add MT6315 settings.
- Configure PMIC PMIF for MT6315.
BUG=b:249436110
TEST=build pass.
BRANCH=corsola
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8186/pmif_spmi.c')
| -rw-r--r-- | src/soc/mediatek/mt8186/pmif_spmi.c | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8186/pmif_spmi.c b/src/soc/mediatek/mt8186/pmif_spmi.c new file mode 100644 index 0000000000..28ea739abd --- /dev/null +++ b/src/soc/mediatek/mt8186/pmif_spmi.c @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#include <device/mmio.h> +#include <soc/pll.h> +#include <soc/pmif_spmi.h> +#include <console/console.h> + +/* IOCFG_LT, DRV_CFG2 */ +DEFINE_BITFIELD(SPMI_SCL, 14, 12) +DEFINE_BITFIELD(SPMI_SDA, 17, 15) +DEFINE_BIT(SPMI_SCL_IN, 27) +DEFINE_BIT(SPMI_SDA_IN, 28) +DEFINE_BIT(SPMI_SCL_PU, 11) +DEFINE_BIT(SPMI_SDA_PD, 12) +DEFINE_BIT(SPMI_SCL_SMT, 28) +DEFINE_BIT(SPMI_SDA_SMT, 28) +DEFINE_BITFIELD(SPMI_TD, 19, 16) +DEFINE_BITFIELD(SPMI_RD, 15, 14) +DEFINE_BITFIELD(SPMI_DRI, 5, 3) + +/* TOPRGU, WDT_SWSYSRST2 */ +DEFINE_BIT(SPMI_MST_RST, 23) +DEFINE_BITFIELD(UNLOCK_KEY, 31, 24) + +/* TOPCKGEN, CLK_CFG_17 */ +DEFINE_BITFIELD(CLK_SPMI_MST_SEL, 10, 8) +DEFINE_BIT(CLK_SPMI_MST_INT, 12) +DEFINE_BIT(PDN_SPMI_MST, 15) + +/* TOPCKGEN, CLK_CFG_UPDATE2 */ +DEFINE_BIT(SPMI_MST_CK_UPDATE, 5) + +const struct spmi_device spmi_dev[] = { + { + .slvid = SPMI_SLAVE_6, + .type = BUCK_CPU, + .type_id = BUCK_CPU_ID, + }, +}; + +const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev); + +int spmi_config_master(void) +{ + /* Software reset */ + SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 1, UNLOCK_KEY, 0x88); + + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_11, + CLK_SPMI_MST_SEL, 0x3, + CLK_SPMI_MST_INT, 0, + PDN_SPMI_MST, 0); + SET32_BITFIELDS(&mtk_topckgen->clk_cfg_update2, SPMI_MST_CK_UPDATE, 1); + + /* Software reset */ + SET32_BITFIELDS(&mtk_rug->wdt_swsysrst2, SPMI_MST_RST, 0, UNLOCK_KEY, 0x88); + + /* Enable SPMI */ + write32(&mtk_spmi_mst->mst_req_en, 1); + write32(&mtk_spmi_mst->rcs_ctrl, 0x15); + + return 0; +} |