diff options
| author | Wenbin Mei <wenbin.mei@mediatek.com> | 2020-09-25 10:03:02 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-16 06:27:12 +0000 |
| commit | 1985894e74711934018f97d082f0b9a9db230894 (patch) | |
| tree | 72b9e7701ec7a040a8b42e27d9ee14a8dfcdd083 /src/soc/mediatek/mt8183/spi.c | |
| parent | 92d59931c42df35358dbeaa090d511d340cb1431 (diff) | |
soc/mediatek/mt8192: ufs: Disable reference clock
UFS reference clock (refclk) is enabled by default, which will cause
the UFSHCI to hold the SPM signal and lead to suspend failure. Since
UFS kernel driver is not built-in, disable refclk in coreboot stage.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8183/spi.c')
0 files changed, 0 insertions, 0 deletions