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authorRex-BC Chen <rex-bc.chen@mediatek.com>2022-10-18 18:59:41 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-10-21 14:57:09 +0000
commita6cd1bd6a89cb92bb0cc0a6cdae4d912644974de (patch)
treeaab8bf18b2523e1ab9b9d46923782c35fe651f22 /src/soc/mediatek/mt8183/pll.c
parent08248c0ce8b270d8ace174e7e2767254c3c2a9ea (diff)
soc/mediatek: Unify PLL function names
For consistency with the PLL function naming: - Rename edp_mux_set_sel() to mt_pll_edp_mux_set_sel(). - Rename mux_set_sel() to pll_mux_set_sel(). BUG=none TEST=build pass. BRANCH=corsola Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ifc7b14bf0db5a5461037e2fbf41756d1542ca945 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68622 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/pll.c')
-rw-r--r--src/soc/mediatek/mt8183/pll.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
index 0e96f4cc68..87562b1e53 100644
--- a/src/soc/mediatek/mt8183/pll.c
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -344,7 +344,7 @@ void mt_pll_init(void)
* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
*/
for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
- mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
+ pll_mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
/* enable [14] dramc_pll104m_ck */
setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);