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authorShelley Chen <shchen@google.com>2024-01-09 17:05:54 -0800
committerShelley Chen <shchen@google.com>2024-01-25 04:13:25 +0000
commit8cae0860e945973b7172ca3757ec775bc3c95d5f (patch)
tree7cbced0f4b1e1078b9484519ccdd0edb099ce9cf /src/soc/mediatek/mt8183/memory.c
parent972cd627a2357f82de93a3987c46a8576af6a3e2 (diff)
mb/google/brox: Switch EC INT and WAKE GPIOs
There was a mistake in the gpio spreadsheet provided by the HW team and the GPIO assignments for the EC INT and WAKE signals got switched from what it was in the schematics. The correct assignments are: GPP_D0 = EC_PCH_INT_ODL GPP_D1 = EC_PCH_WAKE_ODL BUG=b:311450057,b:300690448 BRANCH=None TEST=emerge-brox coreboot Will try to boot OS image on device and see if there are any ec errors. Change-Id: I02057aeb5d82218dbbe4c939d4feb87a4d3da678 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79886 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/mediatek/mt8183/memory.c')
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