diff options
| author | Tristan Shieh <tristan.shieh@mediatek.com> | 2018-09-14 11:12:14 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-10 12:16:43 +0000 |
| commit | 022f76b0d3d571143238b0f8740b0e1d0ee99e3e (patch) | |
| tree | 0c62c286730d0afbe07e1a65e356c5b56cba3160 /src/soc/mediatek/mt8183/include | |
| parent | 38dc00bed15bc70bde14209f730451861a38a393 (diff) | |
mediatek/mt8183: Init PLLs for DRAM
Set up DRAM related PLLs.
And update post divider table to fulfill all freqency settings.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/28667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8183/include')
| -rw-r--r-- | src/soc/mediatek/mt8183/include/soc/pll.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h index 8c0d4e3a2d..5a5f58db3b 100644 --- a/src/soc/mediatek/mt8183/include/soc/pll.h +++ b/src/soc/mediatek/mt8183/include/soc/pll.h @@ -255,6 +255,7 @@ enum { TVDPLL_HZ = 594 * MHz, APLL1_HZ = 180633600, APLL2_HZ = 196608 * KHz, + MPLL_HZ = 208 * MHz, }; /* top_div rate */ |