From 022f76b0d3d571143238b0f8740b0e1d0ee99e3e Mon Sep 17 00:00:00 2001
From: Tristan Shieh <tristan.shieh@mediatek.com>
Date: Fri, 14 Sep 2018 11:12:14 +0800
Subject: mediatek/mt8183: Init PLLs for DRAM

Set up DRAM related PLLs.
And update post divider table to fulfill all freqency settings.

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui

Change-Id: Ic197cef7d31f75ffe4e7d9e73c9cc544719943ab
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-on: https://review.coreboot.org/28667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
---
 src/soc/mediatek/mt8183/include/soc/pll.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/soc/mediatek/mt8183/include')

diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h
index 8c0d4e3a2d..5a5f58db3b 100644
--- a/src/soc/mediatek/mt8183/include/soc/pll.h
+++ b/src/soc/mediatek/mt8183/include/soc/pll.h
@@ -255,6 +255,7 @@ enum {
 	TVDPLL_HZ	= 594 * MHz,
 	APLL1_HZ	= 180633600,
 	APLL2_HZ	= 196608 * KHz,
+	MPLL_HZ		= 208 * MHz,
 };
 
 /* top_div rate */
-- 
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