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authorShaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>2020-12-04 17:00:56 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-01-15 11:29:17 +0000
commit5ff588dbc10bbf69f140cebf3a584f1ed563b1c5 (patch)
treefd72c40c3efe8160bb36f8c70ef14531c949de01 /src/soc/mediatek/mt8183/emi.c
parentf296273692785da1bc88df8d28d955f8d79390e7 (diff)
soc/mediatek/mt8183: Support byte mode and single rank DDR
1. Add emi setting to support byte mode and single rank ddr sample 2. Modify initial setting for DDR with different architecture BUG=b:165768895 BRANCH=kukui TEST=DDR boot up correctly on Kukui Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com> Change-Id: Id2845b2b60e2c447486ee25259dc6a05a0bb619b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8183/emi.c')
-rw-r--r--src/soc/mediatek/mt8183/emi.c30
1 files changed, 22 insertions, 8 deletions
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c
index 8afbef00d8..5e4f01531a 100644
--- a/src/soc/mediatek/mt8183/emi.c
+++ b/src/soc/mediatek/mt8183/emi.c
@@ -157,6 +157,19 @@ static void set_rank_info_to_conf(const struct sdram_params *params)
(is_dual_rank ? 0 : 1) << 12);
}
+void cbt_mrr_pinmux_mapping(void)
+{
+ for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
+ const u8 *map = phy_mapping[chn];
+ write32(&ch[chn].ao.mrr_bit_mux1,
+ (map[8] << 0) | (map[9] << 8) |
+ (map[10] << 16) | (map[11] << 24));
+
+ write32(&ch[chn].ao.mrr_bit_mux2,
+ (map[12] << 0) | (map[13] << 8));
+ }
+}
+
void set_mrr_pinmux_mapping(void)
{
for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
@@ -432,7 +445,7 @@ static void dfs_init_for_calibration(const struct sdram_params *params,
struct dram_shared_data *shared)
{
dramc_init(params, freq_group, shared);
- dramc_apply_config_before_calibration(freq_group);
+ dramc_apply_config_before_calibration(freq_group, params->cbt_mode_extern);
}
static void init_dram(const struct sdram_params *params, u8 freq_group,
@@ -449,7 +462,7 @@ static void init_dram(const struct sdram_params *params, u8 freq_group,
dramc_sw_impedance_cal(params, ODT_ON, &shared->impedance);
dramc_init(params, freq_group, shared);
- dramc_apply_config_before_calibration(freq_group);
+ dramc_apply_config_before_calibration(freq_group, params->cbt_mode_extern);
emi_init2(params);
}
@@ -589,9 +602,10 @@ static int run_calib(const struct dramc_param *dparam,
*first_run = false;
dramc_dbg("Start K (current clock: %u\n", params->frequency);
- if (dramc_calibrate_all_channels(params, freq_group, &shared->mr) != 0)
+ if (dramc_calibrate_all_channels(params, freq_group, &shared->mr,
+ !!(dparam->header.config & DRAMC_CONFIG_DVFS)) != 0)
return -1;
- get_dram_info_after_cal(&density);
+ get_dram_info_after_cal(&density, params->rank_num);
dramc_ac_timing_optimize(freq_group, density);
dramc_dbg("K finished (current clock: %u\n", params->frequency);
@@ -599,10 +613,10 @@ static int run_calib(const struct dramc_param *dparam,
return 0;
}
-static void after_calib(const struct mr_value *mr)
+static void after_calib(const struct mr_value *mr, u32 rk_num)
{
- dramc_apply_config_after_calibration(mr);
- dramc_runtime_config();
+ dramc_apply_config_after_calibration(mr, rk_num);
+ dramc_runtime_config(rk_num);
}
int mt_set_emi(const struct dramc_param *dparam)
@@ -623,6 +637,6 @@ int mt_set_emi(const struct dramc_param *dparam)
if (run_calib(dparam, &shared, DRAM_DFS_SHUFFLE_1, &first_run) != 0)
return -1;
- after_calib(&shared.mr);
+ after_calib(&shared.mr, dparam->freq_params[DRAM_DFS_SHUFFLE_1].rank_num);
return 0;
}