diff options
| author | Tristan Shieh <tristan.shieh@mediatek.com> | 2018-06-06 12:52:20 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-07 07:42:43 +0000 |
| commit | f42db110d0174f05745e3558067d114eae37825b (patch) | |
| tree | a5a52a630e8704369f57d6d21077e95c13733cb7 /src/soc/mediatek/mt8173/dramc_pi_basic_api.c | |
| parent | 794284ff0ee92f7f60c4d33dbf43bf007979389c (diff) | |
mediatek: Refine whitespace and formating changes
This patch fix whitespace and formating issues:
1. Using two spaces between code and single line comment.
2. No space after asterisk.
3. Fix checkpatch error.
4. Remove spaces after cast operators.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/mediatek/mt8173/dramc_pi_basic_api.c')
| -rw-r--r-- | src/soc/mediatek/mt8173/dramc_pi_basic_api.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c index 83ba9995f3..e471b4f312 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c @@ -264,7 +264,7 @@ static void mem_pll_phase_cali(u32 channel) } } - udelay(20); /* delay 20us for external loop pll stable */ + udelay(20); /* delay 20us for external loop pll stable */ /* 2. enable mempll 2 3 4 jitter meter */ for (i = 0; i < 3; i++) @@ -323,7 +323,7 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params) for (channel = 0; channel < CHANNEL_NUM; channel++) mem_pll_init_set_params(channel); - udelay(1); /* wait after da_mpll_sdm_iso_en goes low */ + udelay(1); /* wait after da_mpll_sdm_iso_en goes low */ /* only set once in MPLL */ mt_mem_pll_config_post(); @@ -391,7 +391,7 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params) /* unrequest mempll reset/pdn mode and wait settle */ clrbits_le32(&mt8173_spm->power_on_val0, 0x1 << 27); - udelay(31); /* PLL ready */ + udelay(31); /* PLL ready */ for (channel = 0; channel < CHANNEL_NUM; channel++) mem_pll_init_phase_sync(channel); @@ -402,7 +402,7 @@ void mem_pll_init(const struct mt8173_sdram_params *sdram_params) for (channel = 0; channel < CHANNEL_NUM; channel++) mem_pll_phase_cali(channel); - div2_phase_sync(); /* phase sync for channel B */ + div2_phase_sync(); /* phase sync for channel B */ mt_mem_pll_mux(); } @@ -584,7 +584,7 @@ void dramc_init(u32 channel, const struct mt8173_sdram_params *sdram_params) write32(&ch[channel].ao_regs->padctl4, 0x1 << 2 | 0x1 << 0); - udelay(200); /* tINIT3 > 200us */ + udelay(200); /* tINIT3 > 200us */ write32(&ch[channel].ao_regs->gddr3ctl1, 0x1 << 24 | 0x1 << 20); @@ -682,7 +682,7 @@ void dramc_phy_reset(u32 channel) setbits_le32(&ch[channel].ao_regs->gddr3ctl1, 1 << GDDR3CTL1_RDATRST_SHIFT); - udelay(1); /* delay 1ns */ + udelay(1); /* delay 1ns */ clrbits_le32(&ch[channel].ao_regs->gddr3ctl1, 1 << GDDR3CTL1_RDATRST_SHIFT); |