mt8173: add SPI NOR support

BRANCH=none
BUG=none
TEST=boot oak to kernel on rev1

Change-Id: I0773c81398df445aec16bcfcd0c5a8fe5a588b5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae15c42c2f7d9c2a716e5b6098d85e17279f5eae
Original-Change-Id: I65abf810d35ae5e7156cf6f5730117e690183d18
Original-Signed-off-by: mtk05962 <bayi.cheng@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292693
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 4 insertions, 4 deletions

diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc
index cbc98555fe..97053a5b96 100644
--- a/src/soc/mediatek/mt8173/Makefile.inc
+++ b/src/soc/mediatek/mt8173/Makefile.inc
@@ -16,7 +16,7 @@
 ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y)
 
 bootblock-y += bootblock.c
-bootblock-y += cbfs.c
+bootblock-$(CONFIG_SPI_FLASH) += flash_controller.c
 bootblock-y += pll.c
 bootblock-y += spi.c
 bootblock-y += timer.c
@@ -38,11 +38,11 @@ verstage-$(CONFIG_DRIVERS_UART) += uart.c
 
 verstage-y += timer.c
 verstage-y += wdt.c
-verstage-y += cbfs.c
+verstage-$(CONFIG_SPI_FLASH) += flash_controller.c
 
 ################################################################################
 
-romstage-y += cbfs.c
+romstage-$(CONFIG_SPI_FLASH) += flash_controller.c
 romstage-y += timer.c
 
 romstage-$(CONFIG_DRIVERS_UART) += uart.c
@@ -57,7 +57,7 @@ romstage-y += rtc.c
 
 ramstage-y += cbmem.c
 ramstage-y += spi.c
-ramstage-y += cbfs.c
+ramstage-$(CONFIG_SPI_FLASH) += flash_controller.c
 ramstage-y += soc.c mtcmos.c
 ramstage-y += timer.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c